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to our customers, old company name in catalogs and other documents on april 1 st , 2010, nec electronics corporation merged with renesas technology corporation, and renesas electronics corporation took over all the business of both companies. therefore, although the old company name remains in this document, it is a valid renesas electronics document. we appreciate your understanding. renesas electronics website: http://www.renesas.com april 1 st , 2010 renesas electronics corporation issued by: renesas electronics corporation ( http://www.renesas.com ) send any inquiries to http://www.renesas.com/inquiry .
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h8/3694 group hardware manual 16 users manual rev.5.00 2005.11 renesas 16-bit single-chip microcomputer h8 family/h8/300h tiny series h8/3694n hd64n3694g, HD6483694G, h8/3694f hd64f3694, hd64f3694g, h8/3694 hd6433694, hd6433694g, h8/3693 hd6433693, hd6433693g, h8/3692 hd6433692, hd6433692g, h8/3691 hd6433691, hd6433691g, h8/3690 hd6433690, hd6433690g
rev.5.00 nov. 02, 2005 page ii of xxviii
rev.5.00 nov. 02, 2005 page iii of xxviii 1. these materials are intended as a reference to assist our customers in the selection of the renesas technology corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to renesas technology corp. or a third party. 2. renesas technology corp. assumes no responsibility for any damage, or infringement of any third- party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. all information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by renesas technology corp. without notice due to product improvements or other reasons. it is therefore recommended that customers contact renesas technology corp. or an authorized renesas technology corp. product distributor for the latest product information before purchasing a product listed herein. the information described here may contain technical inaccuracies or typographical errors. renesas technology corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. please also pay attention to information published by renesas technology corp. by various means, including the renesas technology corp. semiconductor home page (http://www.renesas.com). 4. when using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. renesas technology corp. assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. renesas technology corp. semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. please contact renesas technology corp. or an authorized renesas technology corp. product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6. the prior written approval of renesas technology corp. is necessary to reprint or reproduce in whole or in part these materials. 7. if these products or technologies are subject to the japanese export control restrictions, they must be exported under a license from the japanese government and cannot be imported into a country other than the approved destination. any diversion or reexport contrary to the export control laws and regulations of japan and/or the country of destination is prohibited. 8. please contact renesas technology corp. for further details on these materials or the products contained therein. 1. renesas technology corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. trouble with semiconductors may lead to personal injury, fire or property damage. remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. keep safety first in your circuit designs! notes regarding these materials
rev.5.00 nov. 02, 2005 page iv of xxviii general precautions on handling of product 1. treatment of nc pins note: do not connect anything to the nc pins. the nc (not connected) pins are either not connected to any of the internal circuitry or are used as test pins or to reduce noise. if something is connected to the nc pins, the operation of the lsi is not guaranteed. 2. treatment of unused input pins note: fix all unused input pins to high or low level. generally, the input pins of cmos products are high-impedance input pins. if unused pins are in their open states, intermediate levels are induced by noise in the vicinity, a pass- through current flows internally, and a malfunction may occur. 3. processing before initialization note: when power is first supplied, the product?s state is undefined. the states of internal circuits are undefined until full power is supplied throughout the chip and a low level is input on the reset pi n. during the period where the states are undefined, the register settings and the output state of each pin are also undefined. design your system so that it does not malfunction because of processing while it is in this undefined state. for those products which have a reset function, reset the lsi immediately after the power supply has been turned on. 4. prohibition of access to undefined or reserved addresses note: access to undefined or reserved addresses is prohibited. the undefined or reserved addresses may be used to expand functions, or test registers may have been be allocated to these addresse s. do not access these registers; the system?s operation is not guaranteed if they are accessed.
rev.5.00 nov. 02, 2005 page v of xxviii configuration of this manual this manual comprises the following items: 1. general precautions on handling of product 2. configuration of this manual 3. preface 4. contents 5. overview 6. description of functional modules cpu and system-control modules on-chip peripheral modules the configuration of the functional description of each module differs according to the module. however, the generic style includes the following items: i) feature ii) input/output pin iii) register description iv) operation v) usage note when designing an application system that includes this lsi, take notes into account. each section includes notes in relation to the descriptions given, and usage notes are given, as required, as the final part of each section. 7. list of registers 8. electrical characteristics 9. appendix 10. main revisions and additions in this edition (only for revised versions) the list of revisions is a summary of points that have been revised or added to earlier versions. this does not include all of the revised contents . for details, see the actual locations in this manual. 11. index
rev.5.00 nov. 02, 2005 page vi of xxviii preface the h8/3694 group are single-chip microcomputers made up of the high-speed h8/300h cpu employing renesas technology original architectur e as their cores, and th e peripheral functions required to configure a system. the h8/300h cpu ha s an instruction set that is compatible with the h8/300 cpu. target users: this manual was written for users who will be using the h8/3694 group in the design of application systems. target users are expected to understand the fundamentals of electrical circuits, logical circuits, and microcomputers. objective: this manual was written to explain the hardware functions and electrical characteristics of th e h8/3694 group to the target users. refer to the h8/300h series software ma nual for a detailed description of the instruction set. notes on reading this manual: ? in order to understand the overall functions of the chip read the manual according to the contents. this manual can be roughly categorized into parts on the cpu, system control functions, periph eral functions and elect rical characteristics. ? in order to understand the details of the cpu's functions read the h8/300h series software manual. ? in order to understand the details of a register when its name is known read the index that is the final part of the manual to find the page number of the entry on the register. the addresses, bits, and initial values of the registers are summarized in section 20, list of registers. example: bit order: the msb is on the left and the lsb is on the right. notes: when using the on-chip emulator (e7, e8) for h8/3694 program development and debugging, the following restrictions must be noted. 1. the nmi pin is reserved for the e7 or e8, and cannot be used. 2. pins p85, p86, and p87 cannot be used. in order to use these pins, additional hardware must be provided on the user board. 3. area h'7000 to h'7fff is used by the e7 or e8, and is not available to the user. 4. area h'f780 to h'fb7f must on no account be accessed.
rev.5.00 nov. 02, 2005 page vii of xxviii 5. when the e7 or e8 is used, address breaks can be set as either available to the user or for use by the e7 or e8. if address breaks are set as being used by the e7 or e8, the address break control registers must not be accessed. 6. when the e7 or e8 is used, nmi is an input/output pin (open-drain in output mode), p85 and p87 are input pins, and p86 is an output pin. related manuals: the latest versions of all related manuals are available from our web site. please ensure you have the latest versions of all documents you require. http://www.renesas.com/ h8/3694 group manuals: document title document no. h8/3694 group hardware manual this manual h8/300h series software manual rej09b0213 user's manuals for development tools: document title document no. h8s, h8/300 series c/c++ compiler, assembler, optimizing linkage editor user's manual rej10b0058 microcomputer development environment system h8s, h8/300 series simulator/debugger user's manual ade-702-282 h8s, h8/300 series high-performance embedded workshop 3, tutorial rej10b0024 h8s, h8/300 series high-performance embedded workshop 3, user's manual rej10b0026 application notes: document title document no. h8s, h8/300 series c/c++ compiler package application note rej05b0464 single power supply f-ztat tm on-board programming ade-502-055
rev.5.00 nov. 02, 2005 page viii of xxviii
rev.5.00 nov. 02, 2005 page ix of xxviii contents section 1 overview................................................................................................1 1.1 features....................................................................................................................... ........... 1 1.2 internal bloc k diagram......................................................................................................... .4 1.3 pin arrangement ................................................................................................................ .... 6 1.4 pin functions .................................................................................................................. ....... 9 section 2 cpu......................................................................................................13 2.1 address space and memory map ........................................................................................ 14 2.2 register conf igura tion......................................................................................................... 17 2.2.1 general registers.................................................................................................... 18 2.2.2 program counter (pc) ............................................................................................ 19 2.2.3 condition-code re gister (ccr)............................................................................. 19 2.3 data formats................................................................................................................... ..... 21 2.3.1 general register data formats ............................................................................... 21 2.3.2 memory data formats ............................................................................................ 23 2.4 instruction set ................................................................................................................ ...... 24 2.4.1 table of instructions cl assified by function .......................................................... 24 2.4.2 basic instructio n formats ....................................................................................... 33 2.5 addressing modes and effec tive address ca lculation........................................................ 34 2.5.1 addressing modes .................................................................................................. 34 2.5.2 effective address calculation ................................................................................ 38 2.6 basic bus cycle ................................................................................................................ ... 40 2.6.1 access to on-chip me mory (ram, rom)............................................................ 40 2.6.2 on-chip peripheral modules .................................................................................. 41 2.7 cpu states ..................................................................................................................... ...... 42 2.8 usage notes .................................................................................................................... ..... 43 2.8.1 notes on data acce ss to empty areas ................................................................... 43 2.8.2 eepmov instru ction.............................................................................................. 43 2.8.3 bit manipulation instruction................................................................................... 43 section 3 exception handling .............................................................................49 3.1 exception sources and vector address ............................................................................... 49 3.2 register de scriptions .......................................................................................................... .51 3.2.1 interrupt edge select register 1 (iegr1) .............................................................. 51 3.2.2 interrupt edge select register 2 (iegr2) .............................................................. 52 3.2.3 interrupt enable regi ster 1 (ienr1) ...................................................................... 53 3.2.4 interrupt flag register 1 (irr1)............................................................................. 54
rev.5.00 nov. 02, 2005 page x of xxviii 3.2.5 wakeup interrupt flag register (iwpr) ................................................................ 55 3.3 reset exceptio n handling.................................................................................................... 56 3.4 interrupt exception handling .............................................................................................. 57 3.4.1 external interrupts .................................................................................................. 57 3.4.2 internal interrupts ................................................................................................... 58 3.4.3 interrupt handling sequence .................................................................................. 58 3.4.4 interrupt response time......................................................................................... 60 3.5 usage notes .................................................................................................................... ..... 62 3.5.1 interrupts after reset............................................................................................... 62 3.5.2 notes on stack area use ........................................................................................ 62 3.5.3 notes on rewriting port mode registers ............................................................... 62 section 4 address break ..................................................................................... 63 4.1 register de scriptions.......................................................................................................... .63 4.1.1 address break control register (a brkcr) ......................................................... 64 4.1.2 address break status register (a brksr) ............................................................ 65 4.1.3 break address register s (barh, barl).............................................................. 66 4.1.4 break data register s (bdrh, bdrl) ................................................................... 66 4.2 operation ...................................................................................................................... ....... 66 section 5 clock pulse generators ....................................................................... 69 5.1 system clock generator ...................................................................................................... 70 5.1.1 connecting crysta l resona tor ................................................................................ 70 5.1.2 connecting cerami c resonator .............................................................................. 71 5.1.3 external clock input method ................................................................................. 71 5.2 subclock generator............................................................................................................. .72 5.2.1 connecting 32.768-khz cr ystal resonator ............................................................ 72 5.2.2 pin connection when no t using subclock............................................................. 73 5.3 prescalers ..................................................................................................................... ........ 73 5.3.1 prescaler s .............................................................................................................. 73 5.3.2 prescaler w............................................................................................................. 73 5.4 usage notes .................................................................................................................... ..... 74 5.4.1 note on resonators................................................................................................. 74 5.4.2 notes on board design ........................................................................................... 74 section 6 power-down modes............................................................................ 75 6.1 register de scriptions.......................................................................................................... .75 6.1.1 system control regi ster 1 (syscr1) .................................................................... 76 6.1.2 system control regi ster 2 (syscr2) .................................................................... 78 6.1.3 module standby control register 1 (mstcr1) .................................................... 79
rev.5.00 nov. 02, 2005 page xi of xxviii 6.2 mode transitions and states of lsi..................................................................................... 80 6.2.1 sleep mode ............................................................................................................. 83 6.2.2 standby mode......................................................................................................... 83 6.2.3 subsleep mode........................................................................................................ 83 6.2.4 subactive mode ...................................................................................................... 84 6.3 operating frequency in active mode.................................................................................. 84 6.4 direct tr ansition .............................................................................................................. .... 85 6.4.1 direct transition from activ e mode to subactive mode ....................................... 85 6.4.2 direct transition from subac tive mode to ac tive mode ....................................... 85 6.5 module standby function.................................................................................................... 86 section 7 rom ....................................................................................................87 7.1 block confi guratio n............................................................................................................ .87 7.2 register de scriptions .......................................................................................................... .88 7.2.1 flash memory control re gister 1 (flmcr1)........................................................ 89 7.2.2 flash memory control re gister 2 (flmcr2)........................................................ 90 7.2.3 erase block register 1 (ebr1) .............................................................................. 91 7.2.4 flash memory power contro l register (flpwcr) ............................................... 92 7.2.5 flash memory enable register (fenr) ................................................................. 92 7.3 on-board progra mming modes........................................................................................... 93 7.3.1 boot mode .............................................................................................................. 93 7.3.2 programming/erasing in user program mode........................................................ 96 7.4 flash memory prog ramming/erasing .................................................................................. 98 7.4.1 program/program-verify ........................................................................................ 98 7.4.2 erase/erase-verify................................................................................................ 100 7.4.3 interrupt handling when progra mming/erasing flash memory........................... 101 7.5 program/erase pr otection .................................................................................................. 103 7.5.1 hardware protection ............................................................................................. 103 7.5.2 software prot ection............................................................................................... 103 7.5.3 error protec tion..................................................................................................... 103 7.6 programmer mode ............................................................................................................. 104 7.7 power-down states fo r flash memory.............................................................................. 104 section 8 ram ..................................................................................................107 section 9 i/o ports .............................................................................................109 9.1 port 1......................................................................................................................... ......... 109 9.1.1 port mode regist er 1 (pmr1) .............................................................................. 110 9.1.2 port control regist er 1 (pcr1) ............................................................................ 111 9.1.3 port data regist er 1 (pdr1)................................................................................. 111
rev.5.00 nov. 02, 2005 page xii of xxviii 9.1.4 port pull-up control re gister 1 (pucr1)............................................................ 112 9.1.5 pin functio ns ........................................................................................................ 112 9.2 port 2......................................................................................................................... ......... 114 9.2.1 port control regist er 2 (pcr2) ............................................................................ 115 9.2.2 port data regist er 2 (pdr2) ................................................................................ 115 9.2.3 pin functio ns ........................................................................................................ 116 9.3 port 5......................................................................................................................... ......... 117 9.3.1 port mode regist er 5 (pmr5) .............................................................................. 118 9.3.2 port control regist er 5 (pcr5) ............................................................................ 119 9.3.3 port data regist er 5 (pdr5) ................................................................................ 119 9.3.4 port pull-up control re gister 5 (pucr5)............................................................ 120 9.3.5 pin functio ns ........................................................................................................ 120 9.4 port 7......................................................................................................................... ......... 123 9.4.1 port control regist er 7 (pcr7) ............................................................................ 124 9.4.2 port data regist er 7 (pdr7) ................................................................................ 124 9.4.3 pin functio ns ........................................................................................................ 125 9.5 port 8......................................................................................................................... ......... 126 9.5.1 port control regist er 8 (pcr8) ............................................................................ 126 9.5.2 port data regist er 8 (pdr8) ................................................................................ 127 9.5.3 pin functio ns ........................................................................................................ 127 9.6 port b ......................................................................................................................... ........ 130 9.6.1 port data regist er b (pdrb) ............................................................................... 130 section 10 timer a ........................................................................................... 131 10.1 features....................................................................................................................... ....... 131 10.2 input/output pins.............................................................................................................. .132 10.3 register desc riptions......................................................................................................... 1 33 10.3.1 timer mode regist er a (tma)............................................................................ 133 10.3.2 timer counter a (tca) ....................................................................................... 134 10.4 operation ...................................................................................................................... ..... 135 10.4.1 interval timer operation ...................................................................................... 135 10.4.2 clock time base operatio n.................................................................................. 135 10.4.3 clock output......................................................................................................... 135 10.5 usage note..................................................................................................................... .... 135 section 11 timer v ........................................................................................... 137 11.1 features....................................................................................................................... ....... 137 11.2 input/output pins.............................................................................................................. .138 11.3 register desc riptions......................................................................................................... 1 39 11.3.1 timer counter v (tcntv).................................................................................. 139
rev.5.00 nov. 02, 2005 page xiii of xxviii 11.3.2 time constant registers a and b (tcora, tcorb) ........................................ 139 11.3.3 timer control regist er v0 (t crv0) ................................................................... 140 11.3.4 timer control/status regi ster v (tcsrv) .......................................................... 142 11.3.5 timer control regist er v1 (t crv1) ................................................................... 143 11.4 operation ...................................................................................................................... ..... 144 11.4.1 timer v operation................................................................................................ 144 11.5 timer v applicati on examples ......................................................................................... 148 11.5.1 pulse output with arbi trary duty cycle............................................................... 148 11.5.2 pulse output with arbitrary pulse wi dth and delay from trgv input .............. 149 11.6 usage notes .................................................................................................................... ... 150 section 12 timer w ...........................................................................................153 12.1 features....................................................................................................................... ....... 153 12.2 input/output pins .............................................................................................................. .156 12.3 register desc riptions ......................................................................................................... 1 56 12.3.1 timer mode regist er w (tmrw) ....................................................................... 157 12.3.2 timer control regist er w (tcrw) ..................................................................... 158 12.3.3 timer interrupt enable re gister w (tierw) ...................................................... 159 12.3.4 timer status regist er w (tsrw) ........................................................................ 160 12.3.5 timer i/o control regi ster 0 (tio r0) ................................................................. 161 12.3.6 timer i/o control regi ster 1 (tio r1) ................................................................. 163 12.3.7 timer counter (tcnt)......................................................................................... 164 12.3.8 general registers a to d (gra to grd)............................................................. 164 12.4 operation ...................................................................................................................... ..... 165 12.4.1 normal operation ................................................................................................. 165 12.4.2 pwm opera tion.................................................................................................... 169 12.5 operation timing............................................................................................................... 174 12.5.1 tcnt count timing ............................................................................................ 174 12.5.2 output compare output timing ........................................................................... 174 12.5.3 input capture timing............................................................................................ 175 12.5.4 timing of counter clearin g by compare match .................................................. 176 12.5.5 buffer operatio n timing ...................................................................................... 176 12.5.6 timing of imfa to imfd flag setting at comp are matc h.................................. 177 12.5.7 timing of imfa to imfd se tting at input capture ............................................. 178 12.5.8 timing of status flag clearing............................................................................. 178 12.6 usage notes .................................................................................................................... ... 179 section 13 watchdog timer ..............................................................................183 13.1 features....................................................................................................................... ....... 183 13.2 register desc riptions ......................................................................................................... 1 84
rev.5.00 nov. 02, 2005 page xiv of xxviii 13.2.1 timer control/status regi ster wd (tcsrwd) .................................................. 184 13.2.2 timer counter wd (tcwd)................................................................................ 185 13.2.3 timer mode register wd (tmwd) .................................................................... 186 13.3 operation ...................................................................................................................... ..... 187 section 14 serial communication interface 3 (sci3)....................................... 189 14.1 features....................................................................................................................... ....... 189 14.2 input/output pins.............................................................................................................. .191 14.3 register desc riptions......................................................................................................... 1 91 14.3.1 receive shift regi ster (rsr) ............................................................................... 192 14.3.2 receive data regi ster (rdr)............................................................................... 192 14.3.3 transmit shift regi ster (tsr) .............................................................................. 192 14.3.4 transmit data regi ster (tdr).............................................................................. 192 14.3.5 serial mode regi ster (smr) ................................................................................ 193 14.3.6 serial control regi ster 3 (scr3) ......................................................................... 194 14.3.7 serial status regi ster (ssr) ................................................................................. 196 14.3.8 bit rate regist er (brr) ....................................................................................... 198 14.4 operation in asynch ronous mode ..................................................................................... 205 14.4.1 clock..................................................................................................................... 205 14.4.2 sci3 initiali zation................................................................................................. 206 14.4.3 data transmission ................................................................................................ 207 14.4.4 serial data reception ........................................................................................... 209 14.5 operation in clocked synchronous mode ......................................................................... 213 14.5.1 clock..................................................................................................................... 213 14.5.2 sci3 initiali zation................................................................................................. 213 14.5.3 serial data tr ansmission ...................................................................................... 214 14.5.4 serial data reception (clock ed synchronous mode) .......................................... 217 14.5.5 simultaneous serial data tr ansmission and reception........................................ 219 14.6 multiprocessor communi cation func tion.......................................................................... 221 14.6.1 multiprocessor serial da ta transmission ............................................................. 222 14.6.2 multiprocessor serial data reception .................................................................. 224 14.7 interrupts..................................................................................................................... ....... 228 14.8 usage notes .................................................................................................................... ... 229 14.8.1 break detection an d processing ........................................................................... 229 14.8.2 mark state and br eak sending ............................................................................. 229 14.8.3 receive error flags and transmit operations (clocked synchronous mode only) ..................................................................... 229 14.8.4 receive data sampling timing and reception margin in asynchronous mode......................................................................................... 230
rev.5.00 nov. 02, 2005 page xv of xxviii section 15 i 2 c bus interface 2 (iic2) ................................................................231 15.1 features....................................................................................................................... ....... 231 15.2 input/output pins .............................................................................................................. .233 15.3 register desc riptions ......................................................................................................... 2 33 15.3.1 i 2 c bus control regist er 1 (iccr1 )..................................................................... 234 15.3.2 i 2 c bus control regist er 2 (iccr2 )..................................................................... 236 15.3.3 i 2 c bus mode regist er (icmr)............................................................................ 237 15.3.4 i 2 c bus interrupt enable register (i cier) ........................................................... 239 15.3.5 i 2 c bus status regi ster (icsr)............................................................................. 241 15.3.6 slave address regi ster (sar).............................................................................. 244 15.3.7 i 2 c bus transmit data re gister (icdrt)............................................................. 245 15.3.8 i 2 c bus receive data re gister (icd rr).............................................................. 245 15.3.9 i 2 c bus shift regist er (icdrs)............................................................................ 245 15.4 operation ...................................................................................................................... ..... 246 15.4.1 i 2 c bus format...................................................................................................... 246 15.4.2 master transmit operation ................................................................................... 247 15.4.3 master receive operation..................................................................................... 249 15.4.4 slave transmit op eration ..................................................................................... 251 15.4.5 slave receive op eration....................................................................................... 253 15.4.6 clocked synchronous serial format..................................................................... 255 15.4.7 noise can celer...................................................................................................... 257 15.4.8 example of use..................................................................................................... 258 15.5 interrupt request.............................................................................................................. .. 262 15.6 bit synchronous circuit..................................................................................................... 263 15.7 usage notes .................................................................................................................... ... 264 15.7.1 issue (retransmission) of start/stop condi tions .................................................. 264 15.7.2 wait setting in i 2 c bus mode regist er (icmr) ................................................ 264 section 16 a/d converter..................................................................................265 16.1 features....................................................................................................................... ....... 265 16.2 input/output pins .............................................................................................................. .267 16.3 register desc riptions ......................................................................................................... 2 68 16.3.1 a/d data registers a to d (addra to addrd) .............................................. 268 16.3.2 a/d control/status re gister (adcsr) ................................................................ 269 16.3.3 a/d control regist er (adcr) ............................................................................. 270 16.4 operation ...................................................................................................................... ..... 271 16.4.1 single mode.......................................................................................................... 271 16.4.2 scan mode ............................................................................................................ 271 16.4.3 input sampling and a/d conversion time .......................................................... 272 16.4.4 external trigger input timi ng.............................................................................. 273
rev.5.00 nov. 02, 2005 page xvi of xxviii 16.5 a/d conversion accura cy definitions .............................................................................. 274 16.6 usage notes .................................................................................................................... ... 276 16.6.1 permissible signal s ource impedance .................................................................. 276 16.6.2 influences on abso lute accuracy ......................................................................... 276 section 17 eeprom......................................................................................... 277 17.1 features....................................................................................................................... ....... 277 17.2 input/output pins.............................................................................................................. .279 17.3 register desc ription .......................................................................................................... 2 79 17.3.1 eeprom key regist er (ekr)............................................................................. 279 17.4 operation ...................................................................................................................... ..... 280 17.4.1 eeprom inte rface............................................................................................... 280 17.4.2 bus format and timing ........................................................................................ 280 17.4.3 start cond ition ...................................................................................................... 280 17.4.4 stop cond ition ...................................................................................................... 281 17.4.5 acknowledge ........................................................................................................ 281 17.4.6 slave addressing .................................................................................................. 281 17.4.7 write operations................................................................................................... 283 17.4.8 acknowledge polling............................................................................................ 284 17.4.9 read opera tion ..................................................................................................... 285 17.5 usage notes .................................................................................................................... ... 288 17.5.1 data protection at v cc on/off............................................................................... 288 17.5.2 write/erase en durance ......................................................................................... 288 17.5.3 noise suppress ion time ....................................................................................... 288 section 18 power-on reset and low-volta ge detection circuits (optional).. 289 18.1 features....................................................................................................................... ....... 289 18.2 register desc riptions......................................................................................................... 2 90 18.2.1 low-voltage-detection contro l register (l vdcr)............................................ 290 18.2.2 low-voltage-detection status register (lvdsr)............................................... 292 18.3 operation ...................................................................................................................... ..... 293 18.3.1 power-on reset circuit ........................................................................................ 293 18.3.2 low-voltage detec tion circuit............................................................................. 294 section 19 power supply circuit ...................................................................... 299 19.1 when using internal power su pply step-down circuit ................................................... 299 19.2 when not using internal power supply step-dow n circuit............................................. 300 section 20 list of registers............................................................................... 301 20.1 register addresses (a ddress order).................................................................................. 302
rev.5.00 nov. 02, 2005 page xvii of xxviii 20.2 register bits.................................................................................................................. ..... 307 20.3 registers states in ea ch operating mode.......................................................................... 311 section 21 electrica l characteristics .................................................................315 21.1 absolute maximum ratings .............................................................................................. 315 21.2 electrical characteristics (f-ztat? version, eeprom stacked f-ztat tm version).......................................... 315 21.2.1 power supply voltage an d operating ranges ...................................................... 315 21.2.2 dc character istics ................................................................................................ 318 21.2.3 ac character istics ................................................................................................ 324 21.2.4 a/d converter char acteristic s .............................................................................. 328 21.2.5 watchdog timer ch aracteristic s........................................................................... 329 21.2.6 flash memory char acteristi cs .............................................................................. 330 21.2.7 eeprom character istics...................................................................................... 332 21.2.8 power-supply-voltage detection circ uit characteristics (optional) ................... 333 21.2.9 power-on reset circuit char acteristics (opt ional) .............................................. 334 21.3 electrical characteristics (mask-rom version, eeprom stack ed mask-rom version)....................................... 334 21.3.1 power supply voltage an d operating ranges ...................................................... 334 21.3.2 dc character istics ................................................................................................ 337 21.3.3 ac character istics ................................................................................................ 343 21.3.4 a/d converter char acteristic s .............................................................................. 347 21.3.5 watchdog timer ch aracteristic s........................................................................... 348 21.3.6 eeprom character istics...................................................................................... 349 21.3.7 power-supply-voltage detection circ uit characteristics (optional) ................... 350 21.3.8 power-on reset circuit char acteristics (opt ional) .............................................. 351 21.4 operation timing............................................................................................................... 351 21.5 output load condition ...................................................................................................... 354 appendix a instruction set ...............................................................................355 a.1 instruction list............................................................................................................... .... 355 a.2 operation code map.......................................................................................................... 370 a.3 number of execu tion stat es .............................................................................................. 373 a.4 combinations of instructions and addressing modes ....................................................... 384 appendix b i/o port block diagrams ...............................................................385 b.1 i/o port block diagrams.................................................................................................... 385 b.2 port states in each operating st ate ................................................................................... 401 appendix c product code lineup.....................................................................402
rev.5.00 nov. 02, 2005 page xviii of xxviii appendix d package dimensions ..................................................................... 405 appendix e eeprom stacked-structure cross-sectional view ..................... 410 main revisions and additions in this edition..................................................... 411 index .................................................................................................................. 415
rev.5.00 nov. 02, 2005 page xix of xxviii figures section 1 overview figure 1.1 internal block diagram of h8/3694 group of f-ztat tm and mask-rom versions.. 4 figure 1.2 internal block diagram of h8/3694n (eeprom stacked version) ............................ 5 figure 1.3 pin arrangement of h8/3694 group of f-ztat tm and mask-rom versions (fp-64e, fp-64a).......................................................................................................... 6 figure 1.4 pin arrangement of h8/3694 group of f-ztat tm and mask-rom versions (fp-48f, fp-48b, tnp-48)............................................................................................ 7 figure 1.5 pin arrangement of h8/3694 n (eeprom stacked version) (fp-64e)....................... 8 section 2 cpu figure 2.1 memory map (1) .................................................................................................... ..... 14 figure 2.1 memory map (2) .................................................................................................... ..... 15 figure 2.1 memory map (3) .................................................................................................... ..... 16 figure 2.2 cpu regi sters ..................................................................................................... ........ 17 figure 2.3 usage of general registers ........................................................................................ .18 figure 2.4 relationship between stack pointer an d stack area ................................................... 19 figure 2.5 general regi ster data formats (1).............................................................................. 21 figure 2.5 general regi ster data formats (2).............................................................................. 22 figure 2.6 memo ry data formats............................................................................................... .. 23 figure 2.7 inst ruction formats............................................................................................... ....... 34 figure 2.8 branch address specifi cation in memory indirect mode ........................................... 37 figure 2.9 on-chip memory acces s cycle.................................................................................. 40 figure 2.10 on-chip peripheral mo dule access cycle (3 -state access)..................................... 41 figure 2.11 cp u operation states............................................................................................. ... 42 figure 2.12 state tran siti ons ................................................................................................ ........ 43 figure 2.13 example of timer configuration with two registers allocated to same address .. 44 section 3 exception handling figure 3.1 reset se quence.................................................................................................... ........ 58 figure 3.2 stack status after exceptio n handling ........................................................................ 60 figure 3.3 interrupt sequence................................................................................................ ....... 61 figure 3.4 port mode regi ster setting and interrupt reques t flag clearing procedure .............. 62 section 4 address break figure 4.1 block diag ram of address break................................................................................ 63 figure 4.2 address break inte rrupt operation example (1)......................................................... 67 figure 4.2 address break inte rrupt operation example (2)......................................................... 67
rev.5.00 nov. 02, 2005 page xx of xxviii section 5 clock pulse generators figure 5.1 block diagram of clock pulse generators.................................................................. 69 figure 5.2 block diagram of system clock generator ................................................................ 70 figure 5.3 typical connect ion to crystal resonator.................................................................... 70 figure 5.4 equivalent circ uit of crystal resonator...................................................................... 70 figure 5.5 typical connect ion to ceramic resonator.................................................................. 71 figure 5.6 example of external clock input ................................................................................ 71 figure 5.7 block diagram of subclock generator ....................................................................... 72 figure 5.8 typical connection to 32.768-khz crysta l resonator................................................ 72 figure 5.9 equivalent circuit of 32.768-khz crys tal resona tor.................................................. 72 figure 5.10 pin connectio n when not using subclock ................................................................ 73 figure 5.11 example of incorrect board design ........................................................................... 74 section 6 power-down modes figure 6.1 mode transition diagram ........................................................................................... 80 section 7 rom figure 7.1 flash memory block config uration............................................................................ 88 figure 7.2 programming/erasing flowch art example in user program mode............................ 97 figure 7.3 program/prog ram-verify flowchart ........................................................................... 99 figure 7.4 erase/eras e-verify flowchart ................................................................................... 102 section 9 i/o ports figure 9.1 port 1 pin config uration.......................................................................................... .. 109 figure 9.2 port 2 pin config uration.......................................................................................... .. 114 figure 9.3 port 5 pin config uration.......................................................................................... .. 117 figure 9.4 port 7 pin config uration.......................................................................................... .. 123 figure 9.5 port 8 pin config uration.......................................................................................... .. 126 figure 9.6 port b pin config uration.......................................................................................... .130 section 10 timer a figure 10.1 block di agram of timer a ..................................................................................... 132 section 11 timer v figure 11.1 block di agram of timer v ..................................................................................... 138 figure 11.2 increment timi ng with intern al clock .................................................................... 145 figure 11.3 increment timi ng with extern al clock................................................................... 145 figure 11.4 ovf set timing ................................................................................................... ... 145 figure 11.5 cmfa an d cmfb set timing................................................................................ 146 figure 11.6 tmov output timing ............................................................................................ 146 figure 11.7 clear timi ng by compare match............................................................................ 146 figure 11.8 clear ti ming by tmriv input ............................................................................... 147
rev.5.00 nov. 02, 2005 page xxi of xxviii figure 11.9 pulse output example ............................................................................................. 148 figure 11.10 example of pulse outp ut synchronized to trgv input....................................... 149 figure 11.11 contention betw een tcntv write and clear ...................................................... 150 figure 11.12 contention between tcora write and co mpare match ..................................... 151 figure 11.13 internal clock sw itching and tcntv operation ................................................. 151 section 12 timer w figure 12.1 timer w block diagram ......................................................................................... 155 figure 12.2 free-runnin g counter operation ............................................................................ 166 figure 12.3 periodic counter operation..................................................................................... 16 6 figure 12.4 0 and 1 output example (toa = 0, tob = 1)........................................................ 167 figure 12.5 toggle output example (toa = 0, tob = 1) ........................................................ 167 figure 12.6 toggle output example (toa = 0, tob = 1) ........................................................ 167 figure 12.7 input capt ure operating example........................................................................... 168 figure 12.8 buffer operatio n example (input capture)............................................................. 169 figure 12.9 pwm mo de example (1) ........................................................................................ 170 figure 12.10 pwm m ode example (2) ...................................................................................... 170 figure 12.11 buffer operatio n example (outpu t compare) ...................................................... 171 figure 12.12 pwm mode example (tob, toc, and tod = 0: initial out put values are set to 0) ............................... 172 figure 12.13 pwm mode example (tob, toc, and tod = 1: initial out put values are set to 1) ............................... 173 figure 12.14 count timing fo r internal cloc k source ............................................................... 174 figure 12.15 count timing fo r external cloc k source.............................................................. 174 figure 12.16 output co mpare output timing ........................................................................... 175 figure 12.17 input capt ure input signa l timing........................................................................ 175 figure 12.18 timing of counte r clearing by comp are matc h................................................... 176 figure 12.19 buffer operat ion timing (compa re match).......................................................... 176 figure 12.20 buffer operat ion timing (input capture) ............................................................. 177 figure 12.21 timing of imfa to im fd flag setting at compare match .................................. 177 figure 12.22 timing of imfa to im fd flag setting at input capture...................................... 178 figure 12.23 timing of stat us flag clearing by cpu................................................................ 178 figure 12.24 contention betw een tcnt write and clear ......................................................... 179 figure 12.25 internal clock sw itching and tcnt operation.................................................... 180 figure 12.26 when compare match and bit manipulation instruction to tcrw occur at the same timing ..................................................................................... 181 section 13 watchdog timer figure 13.1 block diagra m of watchdog timer ........................................................................ 183 figure 13.2 watchdog ti mer operation example...................................................................... 187
rev.5.00 nov. 02, 2005 page xxii of xxviii section 14 serial commu nication interface 3 (sci3) figure 14.1 bloc k diagram of sci3........................................................................................... 1 90 figure 14.2 data format in asynchronous co mmunication ...................................................... 205 figure 14.3 relationship between output clock and transfer data phase (asynchronous mode) (example with 8-b it data, parity, two stop bits) ............. 205 figure 14.4 sample sci3 initialization fl owchart ..................................................................... 206 figure 14.5 example sci3 operation in transmission in asynchronous mode (8-bit data, parity, one stop bit) ........................................................................... 207 figure 14.6 sample serial transmi ssion flowchart (async hronous mode) .............................. 208 figure 14.7 example sci3 operatio n in reception in asynchronous mode (8-bit data, parity, one stop bit) ........................................................................... 209 figure 14.8 sample serial data recep tion flowchart (asynchronous mode) (1)...................... 211 figure 14.8 sample serial reception data flow chart (2) .......................................................... 212 figure 14.9 data format in cl ocked synchronous communication .......................................... 213 figure 14.10 example of sci3 operation in transmission in clocked synchronous mode...... 215 figure 14.11 sample serial transmission flowchart (clocked sy nchronous mode) ................ 216 figure 14.12 example of sci3 reception operation in clocked synchronous mode............... 217 figure 14.13 sample serial reception fl owchart (clocked sync hronous mo de)...................... 218 figure 14.14 sample flowchart of simultaneous serial transmit and receive operations (clo cked synchronous mode) ........................................ 220 figure 14.15 example of communication using multiprocessor format (transmission of data h'aa to receiving st ation a) .......................................... 222 figure 14.16 sample multiprocessor serial transmissi on flowchart ........................................ 223 figure 14.17 sample multiprocessor serial reception fl owchart (1)........................................ 225 figure 14.17 sample multiprocessor serial reception fl owchart (2)........................................ 226 figure 14.18 example of sci3 operatio n in reception using mu ltiprocessor format (example with 8-bit data, multipro cessor bit, one stop bit) .............................. 227 figure 14.19 receive data sampli ng timing in asynchronous mode ...................................... 230 section 15 i 2 c bus interface 2 (iic2) figure 15.1 block diagram of i 2 c bus interf ace 2..................................................................... 232 figure 15.2 external circu it connections of i/o pins ................................................................ 233 figure 15.3 i 2 c bus form ats ...................................................................................................... 246 figure 15.4 i 2 c bus timi ng........................................................................................................ 246 figure 15.5 master transmit mode operation timing (1)......................................................... 248 figure 15.6 master transmit mode operation timing (2)......................................................... 248 figure 15.7 master receive mode operation timing (1) .......................................................... 250 figure 15.8 master receive mode operation timing (2) .......................................................... 251 figure 15.9 slave transmit mode operation timing (1) ........................................................... 252 figure 15.10 slave transmit mode operation timing (2) ......................................................... 253
rev.5.00 nov. 02, 2005 page xxiii of xxviii figure 15.11 slave receive mode operation timing (1)........................................................... 254 figure 15.12 slave receive mode operation timing (2)........................................................... 254 figure 15.13 clocked synchron ous serial transfer format....................................................... 255 figure 15.14 transmit mode operatio n timing......................................................................... 256 figure 15.15 receive mo de operation timing .......................................................................... 257 figure 15.16 block diag ram of noise conceler......................................................................... 257 figure 15.17 sample flowchar t for master tr ansmit mode....................................................... 258 figure 15.18 sample flowchar t for master r eceive mode ........................................................ 259 figure 15.19 sample flowchar t for slave tran smit mode......................................................... 260 figure 15.20 sample flowch art for slave r eceive mode .......................................................... 261 figure 15.21 the timing of th e bit synchronou s circuit .......................................................... 263 section 16 a/d converter figure 16.1 block diag ram of a/d c onverter ........................................................................... 266 figure 16.2 a/d conversion timing .......................................................................................... 27 2 figure 16.3 external trigger input timing ................................................................................ 273 figure 16.4 a/d conversion accuracy definitions (1) .............................................................. 275 figure 16.5 a/d conversion accuracy definitions (2) .............................................................. 275 figure 16.6 analog i nput circuit ex ample................................................................................. 276 section 17 eeprom figure 17.1 block diagram of eeprom ................................................................................... 278 figure 17.2 eeprom bus format and bus timing .................................................................. 280 figure 17.3 byte write operation ............................................................................................. .283 figure 17.4 page write operation ............................................................................................. .284 figure 17.5 current ad dress read op eration............................................................................. 285 figure 17.6 random ad dress read operation ........................................................................... 286 figure 17.7 sequential read operation (when current address read is used)............................. 287 section 18 power-on reset and lo w-voltage detection circuits (optional) figure 18.1 block diagram of power-on reset circuit and low- voltage detection circuit.... 290 figure 18.2 operational timi ng of power-on rese t circuit...................................................... 294 figure 18.3 operational timing of lvdr circuit ..................................................................... 295 figure 18.4 operational timing of lvdi circuit....................................................................... 296 figure 18.5 timing for operation/releas e of low-voltage det ection circuit .......................... 297 section 19 power supply circuit figure 19.1 power supply connection when internal step-down circuit is used .................... 299 figure 19.2 power supply connection when internal step-down circuit is not used ............. 300 section 21 electrical characteristics figure 21.1 system clock input timing..................................................................................... 351 figure 21.2 res low width timing.......................................................................................... 352
rev.5.00 nov. 02, 2005 page xxiv of xxviii figure 21.3 input timing..................................................................................................... ....... 352 figure 21.4 i 2 c bus interface inpu t/output ti ming ................................................................... 352 figure 21.5 sck3 input clock timing ...................................................................................... 353 figure 21.6 sci input/output timi ng in clocked synchronous mode ...................................... 353 figure 21.7 eepr om bus timing............................................................................................. 354 figure 21.8 outp ut load circuit .............................................................................................. .. 354 appendix b i/o port block diagrams figure b.1 port 1 block diagra m (p17) ..................................................................................... 385 figure b.2 port 1 block diagram (p16 to p14) .......................................................................... 386 figure b.3 port 1 bloc k diagram (p12, p11) ............................................................................. 387 figure b.4 port 1 block diagra m (p10) ..................................................................................... 388 figure b.5 port 2 block diagra m (p22) ..................................................................................... 389 figure b.6 port 2 block diagra m (p21) ..................................................................................... 390 figure b.7 port 2 block diagra m (p20) ..................................................................................... 391 figure b.8 port 5 bloc k diagram (p57, p56) ............................................................................. 392 figure b.9 port 5 block diagra m (p55) ..................................................................................... 393 figure b.10 port 5 bloc k diagram (p54 to p50) ........................................................................ 394 figure b.11 port 7 block diagram (p76) ................................................................................... 395 figure b.12 port 7 block diagram (p75) ................................................................................... 396 figure b.13 port 7 block diagram (p74) ................................................................................... 397 figure b.14 port 8 bloc k diagram (p87 to p85) ........................................................................ 398 figure b.15 port 8 bloc k diagram (p84 to p81) ........................................................................ 399 figure b.16 port 8 block diagram (p80) ................................................................................... 400 figure b.17 port b bloc k diagram (pb7 to pb0) ...................................................................... 401 appendix d package dimensions figure d.1 fp-64e package dimensions ................................................................................... 405 figure d.2 fp-64a package dimensions ................................................................................... 406 figure d.3 fp-48f package dimensions.................................................................................... 407 figure d.4 fp-48b package dimensions ................................................................................... 408 figure d.5 tnp-48 package dimensions................................................................................... 409 appendix e eeprom stacked-structure cross-sectional view figure e.1 eeprom stacked-st ructure cross-sec tional vi ew ................................................. 410
rev.5.00 nov. 02, 2005 page xxv of xxviii tables section 1 overview table 1.1 pin functions ............................................................................................................ 9 section 2 cpu table 2.1 operation notation ................................................................................................. 24 table 2.2 data transfer instructions....................................................................................... 25 table 2.3 arithmetic operations instructions (1) ................................................................... 26 table 2.3 arithmetic operations instructions (2) ................................................................... 27 table 2.4 logic operations instructions................................................................................. 28 table 2.5 shift instru ctions..................................................................................................... 28 table 2.6 bit manipulation inst ructions (1)............................................................................ 29 table 2.6 bit manipulation inst ructions (2)............................................................................ 30 table 2.7 branch instructions ................................................................................................. 31 table 2.8 system control instructions.................................................................................... 32 table 2.9 block data transfer instructions ............................................................................ 33 table 2.10 addressing modes .................................................................................................. 35 table 2.11 absolute address access ranges ........................................................................... 36 table 2.12 effective address ca lculation (1)........................................................................... 38 table 2.12 effective address ca lculation (2)........................................................................... 39 section 3 exception handling table 3.1 exception sources and vector address .................................................................. 49 table 3.2 interrupt wait states ............................................................................................... 60 section 4 address break table 4.1 access and data bus used ..................................................................................... 65 section 5 clock pulse generators table 5.1 crystal resonato r parameters ................................................................................. 71 section 6 power-down modes table 6.1 operating frequency and waiting time................................................................. 77 table 6.2 transition mode after sleep instructio n execution and interrupt handling ........ 81 table 6.3 internal state in ea ch operating mode................................................................... 82 section 7 rom table 7.1 setting programming modes .................................................................................. 93 table 7.2 boot mode operation ............................................................................................. 95 table 7.3 system clock frequencies for which automatic adjustment of lsi bit rate is possible ...................................................................................... 96 table 7.4 reprogram data com putation table .................................................................... 100
rev.5.00 nov. 02, 2005 page xxvi of xxviii table 7.5 additional-program data computation table ...................................................... 100 table 7.6 programming time ............................................................................................... 100 table 7.7 flash memory oper ating states............................................................................ 105 section 10 timer a table 10.1 pin configuration.................................................................................................. 132 section 11 timer v table 11.1 pin configuration.................................................................................................. 138 table 11.2 clock signals to input to tc ntv and counting conditions ............................... 141 section 12 timer w table 12.1 timer w functions ............................................................................................... 154 table 12.2 pin configuration.................................................................................................. 156 section 14 serial commu nication interface 3 (sci3) table 14.1 pin configuration.................................................................................................. 191 table 14.2 examples of brr settings for various b it rates (asynchronous mode) (1) ...... 199 table 14.2 examples of brr settings for various b it rates (asynchronous mode) (2) ...... 200 table 14.2 examples of brr settings for various b it rates (asynchronous mode) (3) ...... 201 table 14.3 maximum bit rate for each fre quency (asynchronous mode) .......................... 202 table 14.4 examples of bbr setting for various bit rates (clocked synchronou s mode) (1)......................................................................... 203 table 14.4 examples of brr settings for various bit rates (clocked synchronou s mode) (2)......................................................................... 204 table 14.5 ssr status flags and recei ve data ha ndling ...................................................... 210 table 14.6 sci3 interrupt requests........................................................................................ 228 section 15 i 2 c bus interface 2 (iic2) table 15.1 i 2 c bus interface pins........................................................................................... 233 table 15.2 transfer rate ........................................................................................................ 235 table 15.3 interrupt re quests................................................................................................. 262 table 15.4 time for monitoring scl..................................................................................... 263 section 16 a/d converter table 16.1 pin configuration.................................................................................................. 267 table 16.2 analog input channels and corr esponding addr registers .............................. 268 table 16.3 a/d conversion time (single mode)................................................................... 273 section 17 eeprom table 17.1 pin configuration.................................................................................................. 279 table 17.2 slave addresses .................................................................................................... 282
rev.5.00 nov. 02, 2005 page xxvii of xxviii section 18 power-on reset and lo w-voltage detection circuits (optional) table 18.1 lvdcr settings and se lect func tions................................................................. 292 section 21 electrical characteristics table 21.1 absolute maximum ratings ................................................................................. 315 table 21.2 dc characteris tics (1)........................................................................................... 318 table 21.2 dc characteris tics (2)........................................................................................... 322 table 21.2 dc characteris tics (3)........................................................................................... 323 table 21.3 ac character istics ................................................................................................ 324 table 21.4 i 2 c bus interface timing ...................................................................................... 326 table 21.5 serial communication inte rface (sci) timing..................................................... 327 table 21.6 a/d converter char acteristic s .............................................................................. 328 table 21.7 watchdog timer ch aracteristic s........................................................................... 329 table 21.8 flash memory char acteristic s .............................................................................. 330 table 21.9 eeprom character istics...................................................................................... 332 table 21.10 power-supply-voltage detecti on circuit charact eristics................................. 333 table 21.11 power-on reset circu it characteris tics............................................................ 334 table 21.12 dc characteris tics (1)....................................................................................... 337 table 21.12 dc characteris tics (2)....................................................................................... 341 table 21.12 dc characteris tics (3)....................................................................................... 342 table 21.13 ac character istics ............................................................................................ 343 table 21.14 i 2 c bus interface timing .................................................................................. 345 table 21.15 serial communication inte rface (sci) timing................................................. 346 table 21.16 a/d converter char acteristic s .......................................................................... 347 table 21.17 watchdog timer ch aracteristic s....................................................................... 348 table 21.18 eeprom character istics.................................................................................. 349 table 21.19 power-supply-voltage detecti on circuit charact eristics................................. 350 table 21.20 power-on reset circu it characteris tics............................................................ 351 appendix a instruction set table a.1 instruction set ....................................................................................................... 357 table a.2 operation code map (1) ....................................................................................... 370 table a.2 operation code map (2) ....................................................................................... 371 table a.2 operation code map (3) ....................................................................................... 372 table a.3 number of cycles in each instruction.................................................................. 374 table a.4 number of cycles in each instruction.................................................................. 375 table a.5 combinations of instructions and addressing modes .......................................... 384
rev.5.00 nov. 02, 2005 page xxviii of xxviii
section 1 overview rev.5.00 nov. 02, 2005 page 1 of 418 rej09b0028-0500 section 1 overview 1.1 features ? ? ? ? ? ? ? ? ? ? ? ?
section 1 overview rev.5.00 nov. 02, 2005 page 2 of 418 rej09b0028-0500 ? on-chip memory model product classification standard version on-chip power-on reset and low- voltage detecting circuit version rom ram remarks flash memory version (f-ztat tm version) h8/3694f hd64f3694 hd64f3694g 32 kbytes 2,048 bytes mask rom version h8/3694 hd6433694 hd6433694g 32 kbytes 1,024 bytes h8/3693 hd6433693 hd6433693g 24 kbytes 1,024 bytes h8/3692 hd6433692 hd6433692g 16 kbytes 512 bytes h8/3691 hd6433691 hd6433691g 12 kbytes 512 bytes h8/3690 hd6433690 hd6433690g 8 kbytes 512 bytes flash memory version hd64n3694g 32 kbytes 2,048 bytes eeprom stacked version (512 bytes) mask-rom version h8/3694n HD6483694G 32 kbytes 1,024 bytes ? general i/o ports i/o pins: 29 i/o pins (27 i/o pins for h8/3694n), including 8 large current ports (i ol = 20 ma, @v ol = 1.5 v) input-only pins: 8 input pins (also used for analog input) ? eeprom interface (only for h8/3694n) i 2 c bus interface (conforms to the i 2 c bus interface format that is advocated by philips electronics) ? supports various power-down modes note: f-ztat tm is a trademark of renesas technology corp.
section 1 overview rev.5.00 nov. 02, 2005 page 3 of 418 rej09b0028-0500 ? compact package package code body size pin pitch lqfp-64 fp-64e 10.0 10.0 mm 0.5 mm qfp-64 fp-64a 14.0 14.0 mm 0.8 mm lqfp-48 fp-48f 10.0 10.0 mm 0.65 mm lqfp-48 fp-48b 7.0 7.0 mm 0.5 mm qfn-48 tnp-48 7.0 7.0 mm 0.5 mm only lqfp-64 (fp-64e) for h8/3694n package
section 1 overview rev.5.00 nov. 02, 2005 page 4 of 418 rej09b0028-0500 1.2 internal block diagram p10/tmow p11 p12 p14/ irq0 p15/ irq1 p16/ irq2 p17/ irq3 /trgv p50/ wkp0 p51/ wkp1 p52/ wkp2 p53/ wkp3 p54/ wkp4 p55/ wkp5 / adtr g p56/sda p57/scl pb0/an0 pb1/an1 pb2/an2 pb3/an3 pb4/an4 pb5/an5 pb6/an6 pb7/an7 v cc v ss v cl res test nmi av cc p20/sck3 p21/rxd p22/txd p80/ftci p81/ftioa p82/ftiob p83/ftioc p84/ftiod p85 p86 p87 p74/tmriv p75/tmciv p76/tmov osc1 osc2 x1 x2 cpu h8/300h rom ram sci3 port 1 timer w iic2 timer a watchdog timer timer v a/d converter por/lvd (optional) subclock generator system clock generator port 2 port b port 5 port 7 port 8 data bus (upper) address bus data bus (lower) figure 1.1 internal block diagram of h8/3694 group of f-ztat tm and mask-rom versions
section 1 overview rev.5.00 nov. 02, 2005 page 5 of 418 rej09b0028-0500 p10/tmow p11 p12 p14/ irq0 p15/ irq1 p16/ irq2 p17/ irq3 /trgv p50/ wkp0 p51/ wkp1 p52/ wkp2 p53/ wkp3 p54/ wkp4 p55/ wkp5 / adtr g p56/sda p57/scl pb0/an0 pb1/an1 pb2/an2 pb3/an3 pb4/an4 pb5/an5 pb6/an6 pb7/an7 v cc v ss v cl res test nmi av cc p20/sck3 p21/rxd p22/txd p80/ftci p81/ftioa p82/ftiob p83/ftioc p84/ftiod p85 p86 p87 p74/tmriv p75/tmciv p76/tmov osc1 osc2 x1 x2 cpu h8/300h rom ram sci3 port 1 timer w iic2 por/lvd (optional) timer a watchdog timer timer v a/d converter subclock generator system clock generator port 2 port b port 5 port 7 port 8 data bus (upper) address bus data bus (lower) sda scl note: the hd64n3694g is a stacked-structure product in which an eeprom chip is mounted on the hd64f3694g (f-ztat tm version). the HD6483694G is a stacked-structure product in which an eeprom chip is mounted on the hd6433694g (mask-rom version). eeprom i 2 c bus figure 1.2 internal block diagram of h8/3694n (eeprom stacked version)
section 1 overview rev.5.00 nov. 02, 2005 page 6 of 418 rej09b0028-0500 1.3 pin arrangement nc nc av cc x2 x1 v cl res test v ss osc2 osc1 v cc p50/ wkp0 p51/ wkp1 nc nc 1 2 3 4 5 6 7 8 9 10111213141516 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 nc nc p22/txd p21/rxd p20/sck3 p87 p86 p85 p84/ftiod p83/ftioc p82/ftiob p81/ftioa p80/ftci nmi nc nc 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 nc nc p14/ irq0 p15/ irq1 p16/ irq2 p17/ irq3 /trgv pb4/an4 pb5/an5 pb6/an6 pb7/an7 pb3/an3 pb2/an2 pb1/an1 pb0/an0 nc nc nc nc p76/tmov p75/tmciv p74/tmriv p57/scl p56/sda p12 p11 p10/tmow p55/ wkp5 / adtr g p54/ wkp4 p53/ wkp3 p52/ wkp2 nc nc h8/3694 group top view note: do not connect nc pins (these pins are not connected to the internal circuitry). figure 1.3 pin arrangement of h8/3694 group of f-ztat tm and mask-rom versions (fp-64e, fp-64a)
section 1 overview rev.5.00 nov. 02, 2005 page 7 of 418 rej09b0028-0500 avcc x2 x1 v cl res test v ss osc2 osc1 vcc p50/ wkp0 p51/ wkp1 123456789101112 36 35 34 33 32 31 30 29 28 27 26 25 p22/txd p21/rxd p20/sck3 p87 p86 p85 p84/ftiod p83/ftioc p82/ftiob p81/ftioa p80/ftci nmi 24 23 22 21 20 19 18 17 16 15 14 13 37 38 39 40 41 42 43 44 45 46 47 48 p14/ irq0 p15/ irq1 p16/ irq2 p17/ irq3 /trgv pb4/an4 pb5/an5 pb6/an6 pb7/an7 pb3/an3 pb2/an2 pb1/an1 pb0/an0 p76/tmov p75/tmciv p74/tmriv p57/scl p56/sda p12 p11 p10/tmow p55/ wkp5 / adtr g p54/ wkp4 p53/ wkp3 p52/ wkp2 h8/3694 group top view figure 1.4 pin arrangement of h8/3694 group of f-ztat tm and mask-rom versions (fp-48f, fp-48b, tnp-48)
section 1 overview rev.5.00 nov. 02, 2005 page 8 of 418 rej09b0028-0500 nc nc avcc x2 x1 v cl res test v ss osc2 osc1 vcc p50/ wkp0 p51/ wkp1 nc nc 1 2 3 4 5 6 7 8 9 10111213141516 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 nc nc p22/txd p21/rxd p20/sck3 p87 p86 p85 p84/ftiod p83/ftioc p82/ftiob p81/ftioa p80/ftci nmi nc nc 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 nc nc p14/ irq0 p15/ irq1 p16/ irq2 p17/ irq3 /trgv pb4/an4 pb5/an5 pb6/an6 pb7/an7 pb3/an3 pb2/an2 pb1/an1 pb0/an0 nc nc nc nc p76/tmov p75/tmciv p74/tmriv scl sda p12 p11 p10/tmow p55/ wkp5 / adtr g p54/ wkp4 p53/ wkp3 p52/ wkp2 nc nc h8/3694n top view note: do not connect nc pins. figure 1.5 pin arrangement of h8/3694n (eeprom stacked version) (fp-64e)
section 1 overview rev.5.00 nov. 02, 2005 page 9 of 418 rej09b0028-0500 1.4 pin functions table 1.1 pin functions pin no. type symbol fp-64e fp-64a fp-48f fp-48b tnp-48 i/o functions v cc 12 10 input power supply pin. connect this pin to the system power supply. power source pins v ss 9 7 input ground pin. connect this pin to the system power supply (0v). av cc 3 1 input analog power supply pin for the a/d converter. when the a/d converter is not used, connect this pin to the system power supply. v cl 6 4 input internal step-down power supply pin. connect a capacitor of around 0.1 f between this pin and the vss pin for stabilization. osc1 11 9 input clock pins osc2 10 8 output these pins connect with crystal or ceramic resonator for the system clock, or can be used to input an external clock. see section 5, clock pulse generators, for a typical connection. x1 5 3 input x2 4 2 output these pins connect with a 32.768 khz crystal resonator for the subclock. see section 5, clock pulse generators, for a typical connection. system control res 7 5 input reset pin. the pull-up resistor (typ. 150 k ? ) is incorporated. when driven low, the chip is reset. test 8 6 input test pin. connect this pin to vss. nmi 35 25 input non-maskable interrupt request input pin. be sure to pull-up by a pull-up resistor. interrupt pins irq0 to irq3 51 to 54 37 to 40 input external interrupt request input pins. can select the rising or falling edge. wkp0 to wkp5 13, 14, 19 to 22 11 to 16 input external interrupt request input pins. can select the rising or falling edge.
section 1 overview rev.5.00 nov. 02, 2005 page 10 of 418 rej09b0028-0500 pin no. type symbol fp-64e fp-64a fp-48f fp-48b tnp-48 i/o functions timer a tmow 23 17 output this is an output pin for divided clocks. timer v tmov 30 24 output this is an output pin for waveforms generated by the outpu t compare function. tmciv 29 23 input exter nal event input pin. tmriv 28 22 input counter reset input pin. trgv 54 40 input counter start trigger input pin. timer w ftci 36 26 input external event input pin. ftioa to ftiod 37 to 40 27 to 30 i/o output com pare output/input capture input/ pwm output pin sda 26 * 1 20 i/o iic data i/o pin. can directly drive a bus by nmos open-drain output. i 2 c bus interface (iic) scl 27 * 1 21 i/o (eeprom: input) iic clock i/o pin. can directly drive a bus by nmos open-drain output. txd 46 36 output transmit data output pin rxd 45 35 input receive data input pin serial communi- cation interface (sci) sck3 44 34 i/o clock i/o pin a/d converter an7 to an0 55 to 62 41 to 48 input analog input pin adtrg 22 16 input a/d converter trigger input pin. i/o ports pb7 to pb0 55 to 62 41 to 48 input 8-bit input port. p17 to p14, p12 to p10 51 to 54, 23 to 25 37 to 40 17 to 19 i/o 7-bit i/o port. p22 to p20 44 to 46 34 to 36 i/o 3-bit i/o port. p57 to p50 13, 14, 19 to 22, 26 * 2 , 27 * 2 20, 21, 13 to 16, 11, 12 i/o 8-bit i/o port
section 1 overview rev.5.00 nov. 02, 2005 page 11 of 418 rej09b0028-0500 pin no. type symbol fp-64e fp-64a fp-48f fp-48b tnp-48 i/o functions i/o ports p76 to p74 28 to 30 22 to 24 i/o 3-bit i/o port p87 to p80 36 to 43 26 to 33 i/o 8-bit i/o port. notes: 1. these pins are only available for the i 2 c bus interface in the h8/3694n. since the i 2 c bus is disabled after canceling a reset, the ice bit in iccr1 must be set to 1 by using the program. 2. the p57 and p56 pins are not available in the h8/3694n.
section 1 overview rev.5.00 nov. 02, 2005 page 12 of 418 rej09b0028-0500
section 2 cpu cpu30h2d_000120030300 rev.5.00 nov. 02, 2005 page 13 of 418 rej09b0028-0500 section 2 cpu this lsi has an h8/300h cpu with an internal 32-bit architecture that is upward-compatible with the h8/300cpu, and supports only normal mode, which has a 64-kbyte address space. ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? + ? ? ? ? ? ? ? ? ? ? ? ? ? ?
section 2 cpu rev.5.00 nov. 02, 2005 page 14 of 418 rej09b0028-0500 2.1 address space and memory map the address space of this lsi is 64 kbytes, which includes th e program area and the data area. figures 2.1 show the memory map. interrupt vector on-chip rom (32 kbytes) not used not used (1-kbyte work area for flash memory programming) internal i/o register internal i/o register h'0000 h'0033 h'0034 h'7fff h'f780 h'f730 h'f74f h'fb7f h'ff7f h'ff80 h'fb80 h'ffff hd64f3694, hd64f3694g (flash memory version) hd6433690, hd6433690g (mask rom version) hd6433691, hd6433691g (mask rom version) interrupt vector on-chip rom (8 kbytes) not used on-chip ram (512 bytes) internal i/o register h'0000 h'0033 h'0034 h'fd80 h'ff7f h'ff80 h'ffff h'1fff interrupt vector on-chip rom (12 kbytes) not used not used not used on-chip ram (512 bytes) internal i/o register h'0000 h'0033 h'0034 h'fd80 h'ff7f h'ff80 h'ffff h'2fff internal i/o register h'f730 h'f74f internal i/o register h'f730 h'f74f (1-kbyte user area) on-chip ram (2 kbytes) figure 2.1 memory map (1)
section 2 cpu rev.5.00 nov. 02, 2005 page 15 of 418 rej09b0028-0500 interrupt vector on-chip rom (16 kbytes) on-chip ram (512 bytes) internal i/o register h'0000 h'0033 h'0034 h'3fff h'ff7f h'ff80 h'ffff hd6433694, hd6433694g (mask rom version) hd6433693, hd6433693g (mask rom version) hd6433692, hd6433692g (mask rom version) h'fd80 h'f730 h'f74f h'f730 h'f74f h'f730 h'f74f interrupt vector on-chip rom (24 kbytes) not used not used on-chip ram (1 kbyte) internal i/o register h'0000 h'0033 h'0034 h'5fff h'fb80 h'ff7f h'ff80 h'ffff interrupt vector on-chip rom (32 kbytes) not used not used on-chip ram (1 kbyte) internal i/o register internal i/o register h'0000 h'0033 h'0034 h'7fff h'fb80 h'ff7f h'ff80 h'ffff not used internal i/o register not used internal i/o register figure 2.1 memory map (2)
section 2 cpu rev.5.00 nov. 02, 2005 page 16 of 418 rej09b0028-0500 h'0000 hd64n3694g HD6483694G (on-chip eeprom module) user area (512 bytes) slave address register not used not used h'01ff h'ff09 figure 2.1 memory map (3)
section 2 cpu rev.5.00 nov. 02, 2005 page 17 of 418 rej09b0028-0500 2.2 register configuration the h8/300h cpu has the internal registers shown in figure 2.2. there are two types of registers; general registers and control registers. the control registers are a 24-bit program counter (pc), and an 8-bit condition code register (ccr). pc 23 0 15 0 7 0 7 0 e0 e1 e2 e3 e4 e5 e6 e7 r0h r1h r2h r3h r4h r5h r6h r7h r0l r1l r2l r3l r4l r5l r6l r7l sp: pc: ccr: i: ui: stack pointer program counter condition-code register interrupt mask bit user bit half-carry flag user bit negative flag zero flag overflow flag carry flag er0 er1 er2 er3 er4 er5 er6 er7 iuihunzvc ccr 76543210 h: u: n: z: v: c: general registers (ern) control registers (cr) [legend] (sp) figure 2.2 cpu registers
section 2 cpu rev.5.00 nov. 02, 2005 page 18 of 418 rej09b0028-0500 2.2.1 general registers the h8/300h cpu has eight 32-bit general registers. these general registers are all functionally identical and can be used as both address register s and data registers. when a general register is used as a data register, it can be accessed as a 32-b it, 16-bit, or 8-bit regist er. figure 2.3 illustrates the usage of the general registers. when the genera l registers are used as 32-bit registers or address registers, they are designated by the letters er (er0 to er7). the er registers divide into 16-bit general registers designated by the letters e (e0 to e7) and r (r0 to r7). these registers are functionally equivalent, providing a maximum of sixteen 16-bit registers. the e registers (e0 to e7) are also referred to as extended registers. the r registers divide into 8-bit registers designated by the letters rh (r0h to r7h) and rl (r0l to r7l). these registers are functionally equivalent, providing a maximum of sixteen 8-bit registers. the usage of each register can be selected independently. address registers 32-bit registers 16-bit registers 8-bit registers er registers (er0 to er7) e registers (extended registers) (e0 to e7) r registers (r0 to r7) rh registers (r0h to r7h) rl registers (r0l to r7l) figure 2.3 usage of general registers
section 2 cpu rev.5.00 nov. 02, 2005 page 19 of 418 rej09b0028-0500 general register er7 has the function of stack pointer (sp) in addition to its general-register function, and is used implicitly in exception handling and subroutine calls. figure 2.4 shows the relationship between stack poi nter and the stack area. sp (er7) free area stack area figure 2.4 relationship between stack pointer and stack area 2.2.2 program counter (pc) this 24-bit counter indicates the address of the ne xt instruction the cpu will execute. the length of all cpu instructions is 2 bytes (one word), so the least significant pc bit is ignored. (when an instruction is fetched, the least significant pc bit is regarded as 0). the pc is initialized when the start address is loaded by the vector address generated during reset exception-handling sequence. 2.2.3 condition-code register (ccr) this 8-bit register contains internal cpu status information, including an interrupt mask bit (i) and half-carry (h), negative (n), zero (z), overflow (v ), and carry (c) flags. the i bit is initialized to 1 by reset exception-handling sequence, but other bits are not initialized. some instructions leave flag bits unchanged. op erations can be performed on the ccr bits by the ldc, stc, andc, orc, and xorc instructions. the n, z, v, and c flags are used as branching conditions for conditional branch (bcc) instructions. for the action of each instruction on the flag bits, see appendix a. 1, instruction list.
section 2 cpu rev.5.00 nov. 02, 2005 page 20 of 418 rej09b0028-0500 bit bit name initial value r/w description 7 i 1 r/w interrupt mask bit masks interrupts other than nmi when set to 1. nmi is accepted regardless of the i bit setting. the i bit is set to 1 at the start of an e xception-handling sequence. 6 ui undefined r/w user bit can be written and read by software using the ldc, stc, andc, orc, and xorc instructions. 5 h undefined r/w half-carry flag when the add.b, addx.b, sub.b, subx.b, cmp.b, or neg.b instruction is execut ed, this flag is set to 1 if there is a carry or borrow at bit 3, and cleared to 0 otherwise. when the add.w, sub.w, cmp.w, or neg.w instruction is executed, the h flag is set to 1 if there is a carry or borrow at bit 11, and cleared to 0 otherwise. when the add.l, sub.l, cmp.l, or neg.l instruction is executed, the h fl ag is set to 1 if there is a carry or borrow at bit 27, and cleared to 0 otherwise. 4 u undefined r/w user bit can be written and read by software using the ldc, stc, andc, orc, and xorc instructions. 3 n undefined r/w negative flag stores the value of the most significant bit of data as a sign bit. 2 z undefined r/w zero flag set to 1 to indicate zero data, and cleared to 0 to indicate non-zero data. 1 v undefined r/w overflow flag set to 1 when an arithmetic overflow occurs, and cleared to 0 at other times. 0 c undefined r/w carry flag set to 1 when a carry occurs, and cleared to 0 otherwise. used by: ? add instructions, to indicate a carry ? subtract instructions, to indicate a borrow ? shift and rotate instructi ons, to indicate a carry the carry flag is also used as a bit accumulator by bit manipulation instructions.
section 2 cpu rev.5.00 nov. 02, 2005 page 21 of 418 rej09b0028-0500 2.3 data formats the h8/300h cpu can process 1-bit, 4-bit (bcd), 8-bit (byte), 16-bit (word), and 32-bit (longword) data. bit-manipulation instructions operate on 1-bit data by accessing bit n (n = 0, 1, 2, ?, 7) of byte operand data. the daa and das decimal-adjust instructions treat byte data as two digits of 4-bit bcd data. 2.3.1 general register data formats figure 2.5 shows the data formats in general registers. 7 0 7 0 msb lsb msb lsb 70 4 3 don't care don't care don't care 7 0 4 3 70 don't care 65432 71 0 7 0 don't care 65432 710 don't care rnh rnl rnh rnl rnh rnl data type general register data format byte data byte data 4-bit bcd data 4-bit bcd data 1-bit data 1-bit data upper lower upper lower figure 2.5 general register data formats (1)
section 2 cpu rev.5.00 nov. 02, 2005 page 22 of 418 rej09b0028-0500 15 0 msb lsb 15 0 msb lsb 31 16 msb 15 0 lsb ern: en: rn: rnh: rnl: msb: lsb: general register er general register e general register r general register rh general register rl most significant bit least significant bit data type data format general register word data word data rn en longword data [legend] ern figure 2.5 general register data formats (2)
section 2 cpu rev.5.00 nov. 02, 2005 page 23 of 418 rej09b0028-0500 2.3.2 memory data formats figure 2.6 shows the data formats in memory. the h8/300h cpu can access word data and longword data in memory, however word or longword data must begin at an even address. if an attempt is made to access word or longword data at an odd addr ess, an address error does not occur, however the least significant bit of the address is re garded as 0, so access begins the preceding address. this also applies to instruction fetches. when er7 (sp) is used as an address register to access the stack area, the operand size should be word or longword. 70 76 543210 msb lsb msb msb lsb lsb data type address 1-bit data byte data word data address l address l address 2m address 2m+1 longword data address 2n address 2n+1 address 2n+2 address 2n+3 data format figure 2.6 memory data formats
section 2 cpu rev.5.00 nov. 02, 2005 page 24 of 418 rej09b0028-0500 2.4 instruction set 2.4.1 table of instructions classified by function the h8/300h cpu has 62 instructions. tables 2.2 to 2.9 summarize the instructions in each functional category. the notation used in tables 2.2 to 2.9 is defined below. table 2.1 operation notation symbol description rd general register (destination) * rs general register (source) * rn general register * ern general register (32-bit register or address register) (ead) destination operand (eas) source operand ccr condition-code register n n (negative) flag in ccr z z (zero) flag in ccr v v (overflow) flag in ccr c c (carry) flag in ccr pc program counter sp stack pointer #imm immediate data disp displacement + addition ? subtraction multiplication division logical and logical or logical xor move ? not (logical complement) :3/:8/:16/:24 3-, 8-, 16-, or 24-bit length note: * general registers include 8-bit registers (r0h to r7h, r0l to r7l), 16-bit registers (r0 to r7, e0 to e7), and 32-bit registers/address register (er0 to er7).
section 2 cpu rev.5.00 nov. 02, 2005 page 25 of 418 rej09b0028-0500 table 2.2 data transfer instructions instruction size * function mov b/w/l (eas) rd, rs (ead) moves data between two general registers or between a general register and memory, or moves immediate data to a general register. movfpe b (eas) rd, cannot be used in this lsi. movtpe b rs (eas) cannot be used in this lsi. pop w/l @sp+ rn pops a general register from the stack. pop.w rn is identical to mov.w @sp+, rn. pop.l ern is id entical to mov.l @sp+, ern. push w/l rn @?sp pushes a general register onto the stack. push.w rn is identical to mov.w rn, @?sp. push.l ern is identical to mov.l ern, @?sp. note: * refers to the operand size. b: byte w: word l: longword
section 2 cpu rev.5.00 nov. 02, 2005 page 26 of 418 rej09b0028-0500 table 2.3 arithmetic operations instructions (1) instruction size * function add sub b/w/l rd rs rd, rd #imm rd performs addition or subtraction on da ta in two general registers, or on immediate data and data in a general register (immediate byte data cannot be subtracted from byte dat a in a general register. use the subx or add instruction.) addx subx b rd rs c rd, rd #imm c rd performs addition or subtraction with carry on byte data in two general registers, or on immediate data and data in a general register. inc dec b/w/l rd 1 rd, rd 2 rd increments or decrements a general re gister by 1 or 2. (byte operands can be incremented or decremented by 1 only.) adds subs l rd 1 rd, rd 2 rd, rd 4 rd adds or subtracts the value 1, 2, or 4 to or from data in a 32-bit register. daa das b rd decimal adjust rd decimal-adjusts an addition or subtracti on result in a general register by referring to the ccr to produce 4-bit bcd data. mulxu b/w rd rs rd performs unsigned multiplication on data in two general registers: either 8 bits 8 bits 16 bits or 16 bits 16 bits 32 bits. mulxs b/w rd rs rd performs signed multiplication on data in two general registers: either 8 bits 8 bits 16 bits or 16 bits 16 bits 32 bits. divxu b/w rd rs rd performs unsigned division on data in two general registers: either 16 bits 8 bits 8-bit quotient and 8-bit remainder or 32 bits 16 bits 16-bit quotient and 16-bit remainder. note: * refers to the operand size. b: byte w: word l: longword
section 2 cpu rev.5.00 nov. 02, 2005 page 27 of 418 rej09b0028-0500 table 2.3 arithmetic operations instructions (2) instruction size * function divxs b/w rd rs rd performs signed division on data in two general registers: either 16 bits 8 bits 8-bit quotient and 8-bit remainder or 32 bits 16 bits 16-bit quotient and 16-bit remainder. cmp b/w/l rd ? rs, rd ? #imm compares data in a general regist er with data in another general register or with immediate data, and sets ccr bits according to the result. neg b/w/l 0 ? rd rd takes the two's complement (arith metic complement) of data in a general register. extu w/l rd (zero extension) rd extends the lower 8 bits of a 16-bit register to word size, or the lower 16 bits of a 32-bit register to longword size, by padding with zeros on the left. exts w/l rd (sign extension) rd extends the lower 8 bits of a 16-bit register to word size, or the lower 16 bits of a 32-bit register to longword size, by extending the sign bit. note: * refers to the operand size. b: byte w: word l: longword
section 2 cpu rev.5.00 nov. 02, 2005 page 28 of 418 rej09b0028-0500 table 2.4 logic operations instructions instruction size * function and b/w/l rd rs rd, rd #imm rd performs a logical and operation on a general register and another general register or immediate data. or b/w/l rd rs rd, rd #imm rd performs a logical or operation on a general register and another general register or immediate data. xor b/w/l rd rs rd, rd #imm rd performs a logical exclusive or operation on a general register and another general register or immediate data. not b/w/l ? (rd) (rd) takes the one's complement (logical complement) of general register contents. note: * refers to the operand size. b: byte w: word l: longword table 2.5 shift instructions instruction size * function shal shar b/w/l rd (shift) rd performs an arithmetic shift on general register contents. shll shlr b/w/l rd (shift) rd performs a logical shift on general register contents. rotl rotr b/w/l rd (rotate) rd rotates general register contents. rotxl rotxr b/w/l rd (rotate) rd rotates general register contents through the carry flag. note: * refers to the operand size. b: byte w: word l: longword
section 2 cpu rev.5.00 nov. 02, 2005 page 29 of 418 rej09b0028-0500 table 2.6 bit manipulation instructions (1) instruction size * function bset b 1 ( of ) sets a specified bit in a general register or memory operand to 1. the bit number is specified by 3-bit immediat e data or the lower three bits of a general register. bclr b 0 ( of ) clears a specified bit in a general register or memory operand to 0. the bit number is specified by 3-bit immedi ate data or the lower three bits of a general register. bnot b ? ( of ) ( of ) inverts a specified bit in a general register or memory operand. the bit number is specified by 3-bit immediat e data or the lower three bits of a general register. btst b ? ( of ) z tests a specified bit in a general register or memory operand and sets or clears the z flag accordingly. t he bit number is specified by 3-bit immediate data or the lower three bits of a general register. band biand b b c ( of ) c ands the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag. c ? ( of ) c ands the carry flag with the inverse of a specified bit in a general register or memory operand and stores the result in the carry flag. the bit number is specified by 3-bit immediate data. bor bior b b c ( of ) c ors the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag. c ? ( of ) c ors the carry flag with the inverse of a specified bit in a general register or memory operand and stores the result in the carry flag. the bit number is specified by 3-bit immediate data. note: * refers to the operand size. b: byte
section 2 cpu rev.5.00 nov. 02, 2005 page 30 of 418 rej09b0028-0500 table 2.6 bit manipulation instructions (2) instruction size * function bxor bixor b b c ( of ) c xors the carry flag with a specified bi t in a general register or memory operand and stores the result in the carry flag. c ? ( of ) c xors the carry flag with the inverse of a specified bit in a general register or memory operand and stores the result in the carry flag. the bit number is specified by 3-bit immediate data. bld bild b b ( of ) c transfers a specified bit in a general register or memory operand to the carry flag. ? ( of ) c transfers the inverse of a specified bit in a general register or memory operand to the carry flag. the bit number is specified by 3-bit immediate data. bst bist b b c ( of ) transfers the carry flag value to a specified bit in a general register or memory operand. ? c ( of ) transfers the inverse of the carry flag value to a specified bit in a general register or memory operand. the bit number is specified by 3-bit immediate data. note: * refers to the operand size. b: byte
section 2 cpu rev.5.00 nov. 02, 2005 page 31 of 418 rej09b0028-0500 table 2.7 branch instructions instruction size function bcc * ? branches to a specified address if a specified condition is true. the branching conditions are listed below. mnemonic description condition bra(bt) always (true) always brn(bf) never (false) never bhi high c z = 0 bls low or same c z = 1 bcc(bhs) carry clear (high or same) c = 0 bcs(blo) carry set (low) c = 1 bne not equal z = 0 beq equal z = 1 bvc overflow clear v = 0 bvs overflow set v = 1 bpl plus n = 0 bmi minus n = 1 bge greater or equal n v = 0 blt less than n v = 1 bgt greater than z (n v) = 0 ble less or equal z (n v) = 1 jmp ? branches unconditionally to a specified address. bsr ? branches to a subroutine at a specified address. jsr ? branches to a subroutine at a specified address. rts ? returns from a subroutine note : * bcc is the general name for conditional branch instructions.
section 2 cpu rev.5.00 nov. 02, 2005 page 32 of 418 rej09b0028-0500 table 2.8 system control instructions instruction size * function trapa ? starts trap-instruct ion excepti on handling. rte ? returns from an exception-handling routine. sleep ? causes a transition to a power-down state. ldc b/w (eas) ccr moves the source operand contents to the ccr. the ccr size is one byte, but in transfer from memory, data is read by word access. stc b/w ccr (ead) transfers the ccr contents to a destination location. the condition code register size is one byte, but in transfer to memory, data is written by word access. andc b ccr #imm ccr logically ands the ccr with immediate data. orc b ccr #imm ccr logically ors the ccr with immediate data. xorc b ccr #imm ccr logically xors the ccr with immediate data. nop ? pc + 2 pc only increments the program counter. note: * refers to the operand size. b: byte w: word
section 2 cpu rev.5.00 nov. 02, 2005 page 33 of 418 rej09b0028-0500 table 2.9 block data transfer instructions instruction size function eepmov.b ? if r4l 0 then repeat @er5+ @er6+, r4l?1 r4l until r4l = 0 else next; eepmov.w ? if r4 0 then repeat @er5+ @er6+, r4?1 r4 until r4 = 0 else next; transfers a data block. starting from the address set in er5, transfers data for the number of bytes set in r4l or r4 to the address location set in er6. execution of the next instruction be gins as soon as the transfer is completed. 2.4.2 basic instruction formats h8/300h cpu instructions consist of 2-byte (1-word) units. an instruction consists of an operation field (op), a register field (r), an eff ective address extension (e a), and a condition field (cc). figure 2.7 shows examples of instruction formats. ? ? ? ?
section 2 cpu rev.5.00 nov. 02, 2005 page 34 of 418 rej09b0028-0500 op op rn rm nop, rts, etc. add.b rn, rm, etc. mov.b @(d:16, rn), rm rn rm op ea(disp) op cc ea(disp) bra d:8 (1) operation field only (2) operation field and register fields (3) operation field, register fields, and effective address extension (4) operation field, effective address extension, and condition field figure 2.7 instruction formats 2.5 addressing modes and effective address calculation the following describes the h8/300h cpu. in this lsi, the upper eight bits are ignored in the generated 24-bit address, so the effective address is 16 bits. 2.5.1 addressing modes the h8/300h cpu supports the eight addressing modes listed in table 2.10. each instruction uses a subset of these addressing modes. addressing modes that can be used differ depending on the instruction. for details, refer to appendix a.4, combinations of instructions and addressing modes. arithmetic and logic instructions can use the regi ster direct and immediate modes. data transfer instructions can use all addressing modes except program-counter relative and memory indirect. bit manipulation instructions use register direct, register indirect, or the absolute addressing mode (@aa:8) to specify an operand, and register direct (bset, bclr, bnot, and btst instructions) or immediate (3-bit) addressing mode to specify a bit number in the operand.
section 2 cpu rev.5.00 nov. 02, 2005 page 35 of 418 rej09b0028-0500 table 2.10 addressing modes no. addressing mode symbol 1 register direct rn 2 register indirect @ern 3 register indirect with displa cement @(d:16,ern)/@(d:24,ern) 4 register indirect with post-increment register indirect with pre-decrement @ern+ @?ern 5 absolute address @aa:8/@aa:16/@aa:24 6 immediate #xx: 8/#xx:16/#xx:32 7 program-counter relati ve @(d:8,pc)/@(d:16,pc) 8 memory indirect @@aa:8 register direct?rn the register field of the instruction specifies an 8-, 16-, or 32-bit general register containing the operand. r0h to r7h and r0l to r7l can be specified as 8-bit registers. r0 to r7 and e0 to e7 can be specified as 16-bit registers. er0 to er7 can be specified as 32-bit registers. register indirect?@ern the register field of the instruction code specifies an address register (ern), the lower 24 bits of which contain the address of the operand on memory. register indirect with displacemen t?@(d:16, ern) or @(d:24, ern) a 16-bit or 24-bit displacement cont ained in the instruction is adde d to an address register (ern) specified by the register field of the instruction, and the lower 24 bits of the sum the address of a memory operand. a 16-bit displacemen t is sign-extended when added. register indirect with post-incremen t or pre-decrement?@ern+ or @-ern ? register indirect with post-increment?@ern+ the register field of the instruction code specifies an address register (ern) the lower 24 bits of which contains the address of a memory operand. after the operand is accessed, 1, 2, or 4 is added to the address register contents (32 bits) and the sum is stored in the address register. the value added is 1 for byte access, 2 for word access, or 4 for longwo rd access. for the word or longword access, the register value should be even.
section 2 cpu rev.5.00 nov. 02, 2005 page 36 of 418 rej09b0028-0500 ? register indirect with pre-decrement?@-ern the value 1, 2, or 4 is subtracted from an addr ess register (ern) specified by the register field in the instruction code, and the lower 24 bits of the result is the addres s of a memory operand. the result is also stored in the address register . the value subtracted is 1 for byte access, 2 for word access, or 4 for l ongword access. for the word or lo ngword access, the register value should be even. absolute address?@aa:8, @aa:16, @aa:24 the instruction code contains the absolute addr ess of a memory operand. the absolute address may be 8 bits long (@aa:8), 16 bits long (@aa:16), 24 bits long (@aa:24) for an 8-bit absolute address, the upper 16 bits are all assumed to be 1 (h'ffff). for a 16-bit absolute address the upper 8 bits are a sign extension. a 24-bit absolute addres s can access the entire address space. the access ranges of absolute addr esses for the group of this lsi are those shown in table 2.11, because the upper 8 bits are ignored. table 2.11 absolute address access ranges absolute address access range 8 bits (@aa:8) h'ff00 to h'ffff 16 bits (@aa:16) h'0000 to h'ffff 24 bits (@aa:24) h'0000 to h'ffff immediate?#xx:8, #xx:16, or #xx:32 the instruction contains 8-bit (#xx:8), 16-bit (#xx:16), or 32-bit (#xx:32) immediate data as an operand. the adds, subs, inc, and dec instructions contain immediate data implicitly. some bit manipulation instructions contain 3-bit immediate data in the instruction code, specifying a bit number. the trapa instruction contains 2-bit immediate data in its instruction code, specifying a vector address. program-counter relative?@(d:8, pc) or @(d:16, pc) this mode is used in the bsr instruction. an 8-bi t or 16-bit displacement contained in the instruction is sign-extended and added to the 24-bit pc contents to generate a branch address. the pc value to which the displacement is added is the address of the first byte of the next instruction,
section 2 cpu rev.5.00 nov. 02, 2005 page 37 of 418 rej09b0028-0500 so the possible branching range is ?126 to +128 bytes (?63 to +64 words) or ?32766 to +32768 bytes (?16383 to +16384 words) from the branch instruction. the resulting value should be an even number. memory indirect?@@aa:8 this mode can be used by the jmp and jsr instructions. the instruction code contains an 8-bit absolute address specifying a memo ry operand. this memory operand contains a branch address. the memory operand is accessed by longword access. the first byt e of the memory operand is ignored, generating a 24-bit branch address. figure 2.8 shows how to specify branch address for in memory indirect mode. the upper bits of the absolute address are all assumed to be 0, so the address range is 0 to 255 (h'0000 to h'00ff). note that the first part of the address range is also the exception vector area. specified by @aa:8 branch address dummy figure 2.8 branch a ddress specification in memory indirect mode
section 2 cpu rev.5.00 nov. 02, 2005 page 38 of 418 rej09b0028-0500 2.5.2 effective address calculation table 2.12 indicates how effectiv e addresses are calculated in each addressing mode. in this lsi the upper 8 bits of the ef fective address are ignored in order to generate a 16-bit effective address. table 2.12 effective ad dress calculation (1) no 1 r o p 31 0 23 2 3 registe r indirect with dis placement @(d: 16,ern) or @(d: 24,ern) 4 r o p disp r op rm op rn 3 1 0 0 r o p 2 3 0 31 0 dis p 31 0 31 0 23 0 23 0 addressing mode and instruction format effective address calculation effective address (ea) register direct(rn) general register contents general register contents general register contents general register contents sign extension register indirect(@ern) register indirect with post-increment or pre-decrement register indirect with post-increment @ern+ register indirect with pre-decrement @-ern 1, 2, or 4 1, 2, or 4 operand is general register contents. the value to be added or subtracted is 1 when the operand is byte size, 2 for word size, and 4 for longword size.
section 2 cpu rev.5.00 nov. 02, 2005 page 39 of 418 rej09b0028-0500 table 2.12 effective ad dress calculation (2) no 5 op 23 0 abs @aa:8 7 h'ffff op 23 0 @aa:16 @aa:24 abs 15 16 23 0 o p abs 6 o p imm #xx:8/#xx:16/#xx:32 8 addressing mode and instruction format absolute address immediate effective address calculation effective address (ea) sign extension operand is immediate data. 7 p rogr am- counter re lativ e @ (d:8 ,pc ) @( d:16 ,pc) m em ory indirect @@ aa :8 23 0 di s p 0 23 0 di s p op 23 op 8 abs 23 0 abs h' 0000 7 8 0 1 5 23 0 1 5 h' 00 16 [legend] r, rm, rn: op: disp: imm: abs: register field operation field displacement immediate data absolute address pc contents sign extension memory contents
section 2 cpu rev.5.00 nov. 02, 2005 page 40 of 418 rej09b0028-0500 2.6 basic bus cycle cpu operation is synchronized by a system clock ( ) or a subclock ( sub ). the period from a rising edge of or sub to the next rising edge is called one stat e. a bus cycle consists of two states or three states. the cycle differs depending on whet her access is to on-chip memory or to on-chip peripheral modules. 2.6.1 access to on-chip memory (ram, rom) access to on-chip memory takes place in two states . the data bus width is 16 bits, allowing access in byte or word size. figure 2.9 shows the on-chip me mory access cycle. t 1 state bus cycle t 2 state internal address bus internal read signal internal data bus (read access) internal write signal read data address write data internal data bus (write access) sub or figure 2.9 on-chip memory access cycle
section 2 cpu rev.5.00 nov. 02, 2005 page 41 of 418 rej09b0028-0500 2.6.2 on-chip peripheral modules on-chip peripheral modules are accessed in two states or three states. the data bus width is 8 bits or 16 bits depending on the register. for description on the data bus width and number of accessing states of each register, refer to sect ion 20.1, register addresses (address order). registers with 16-bit data bus width can be accessed by word size only. registers with 8-bit data bus width can be accessed by byte or word size. wh en a register with 8-bit data bus width is accessed by word size, a bus cycle occurs twice. in two-state access, the operation timing is the same as that for on-chip memory. figure 2.10 shows the operation timing in the case of three-state access to an on-chip peripheral module. t 1 state bus cycle internal address bus internal read signal internal data bus (read access) internal write signal read data address internal data bus (write access) t 2 state t 3 state write data sub or figure 2.10 on-chip peripheral mo dule access cycle (3-state access)
section 2 cpu rev.5.00 nov. 02, 2005 page 42 of 418 rej09b0028-0500 2.7 cpu states there are four cpu states: the re set state, program execution st ate, program halt state, and exception-handling state. the program execution state includes active mode and subactive mode. for the program halt state there are a sleep mode, standby mode, and sub-sl eep mode. these states are shown in figure 2.11. figure 2.12 shows the state transitions. for details on program execution state and program halt state, refer to section 6, power-down modes. for details on exception processing, refer to section 3, exception handling. cpu state reset state program execution state program halt state exception- handling state active (high speed) mode subactive mode sleep mode subsleep mode power-down modes the cpu executes successive program instructions at high speed, synchronized by the system clock the cpu executes successive program instructions at reduced speed, synchronized by the subclock a state in which some or all of the chip functions are stopped to conserve power a transient state in which the cpu changes the processing flow due to a reset or an interrupt the cpu is initialized standby mode figure 2.11 cpu operation states
section 2 cpu rev.5.00 nov. 02, 2005 page 43 of 418 rej09b0028-0500 reset state program halt state exception-handling state program execution state reset cleared sleep instruction executed reset occurs interrupt source reset occurs interrupt source exception- handling complete reset occurs figure 2.12 state transitions 2.8 usage notes 2.8.1 notes on data access to empty areas the address space of this lsi includes empty areas in additio n to the rom, ram, and on-chip i/o registers areas available to the user. when da ta is transferred from cpu to empty areas, the transferred data will be lost. this action may al so cause the cpu to malfunction. when data is transferred from an empty ar ea to cpu, the contents of the data cannot be guaranteed. 2.8.2 eepmov instruction eepmov is a block-transfer instru ction and transfers th e byte size of data indicated by r4l, which starts from the address indicated by r5, to the address indicated by r6. set r4l and r6 so that the end address of the des tination address (value of r6 + r4l) does not exceed h'ffff (the value of r6 must not change from h'ffff to h'0000 during execution). 2.8.3 bit manipulation instruction the bset, bclr, bnot, bst, and bist instructions read data from the specified address in byte units, manipulate the data of the target bit, an d write data to the same address again in byte units. special care is required wh en using these instructions in cases where two registers are assigned to the same address or when a bit is directly manipulated for a port or a register containing a write-only bit, becau se this may rewrite data of a bit other than the bit to be manipulated.
section 2 cpu rev.5.00 nov. 02, 2005 page 44 of 418 rej09b0028-0500 bit manipulation for two registers assigned to the same address example 1: bit manipulation for the ti mer load register and timer counter (applicable for timer b and timer c, not for the group of this lsi.) figure 2.13 shows an example of a timer in which two timer registers are assigned to the same address. when a bit manipulation instruction accesses the timer load register and timer counter of a reloadable timer, since these two registers share the same address, the following operations takes place. 1. data is read in byte units. 2. the cpu sets or resets the bit to be manipulated with the bit manipulation instruction. 3. the written data is written again in byte units to the timer load register. the timer is counting, so the value read is not necessarily the same as the value in the timer load register. as a result, bits other than the intended bit in the timer counter may be modified and the modified value may be written to the timer load register. read write count clock timer counter timer load register reload internal data bus figure 2.13 example of timer configuration with two registers allocated to same address example 2: the bset instructio n is executed for port 5. p57 and p56 are input pins, with a low-level signal input at p57 and a high-level signal input at p56. p55 to p50 are output pins and output low-level signals. an example to output a high-level signal at p50 with a bset instruction is shown below.
section 2 cpu rev.5.00 nov. 02, 2005 page 45 of 418 rej09b0028-0500 ? prior to executing bset instruction p57 p56 p55 p54 p53 p52 p51 p50 input/output input input output output output output output output pin state low level high level low level low level low level low level low level low level pcr5 0 0 1 1 1 1 1 1 pdr5 1 0 0 0 0 0 0 0 ? bset instruction executed instruction bset #0, @pdr5 the bset instruction is executed for port 5. ? after executing bset instruction p57 p56 p55 p54 p53 p52 p51 p50 input/output input input output output output output output output pin state low level high level low level low level low level low level low level high level pcr5 0 0 1 1 1 1 1 1 pdr5 0 1 0 0 0 0 0 1 ? description on operation 1. when the bset instruction is exec uted, first the cpu reads port 5. since p57 and p56 are input pins, the cpu read s the pin states (low-l evel and high-level input). p55 to p50 are output pins, so the cpu reads the value in pdr5. in this example pdr5 has a value of h'80, but the value read by the cpu is h'40. 2. next, the cpu sets bit 0 of the read data to 1, changing the pdr5 data to h'41. 3. finally, the cpu writes h'41 to pdr5, completing execution of bset instruction. as a result of the bset instruction, bit 0 in pdr5 becomes 1, and p50 outputs a high-level signal. however, bits 7 and 6 of pdr5 end up with different values. to prevent this problem, store a copy of the pdr5 data in a work area in memory. perform the bit manipulation on the data in the work area, then write this data to pdr5.
section 2 cpu rev.5.00 nov. 02, 2005 page 46 of 418 rej09b0028-0500 ? prior to executing bset instruction mov.b #80, r0l mov.b r0l, @ram0 mov.b r0l, @pdr5 the pdr5 value (h'80) is written to a work area in memory (ram0) as well as to pdr5. p57 p56 p55 p54 p53 p52 p51 p50 input/output input input output output output output output output pin state low level high level low level low level low level low level low level low level pcr5 0 0 1 1 1 1 1 1 pdr5 1 0 0 0 0 0 0 0 ram0 1 0 0 0 0 0 0 0 ? bset instruction executed bset #0, @ram0 the bset instruction is executed designating the pdr5 work area (ram0). ? after executing bset instruction mov.b @ram0, r0l mov.b r0l, @pdr5 the work area (ram0) value is written to pdr5. p57 p56 p55 p54 p53 p52 p51 p50 input/output input input output output output output output output pin state low level high level low level low level low level low level low level high level pcr5 0 0 1 1 1 1 1 1 pdr5 1 0 0 0 0 0 0 1 ram0 1 0 0 0 0 0 0 1 bit manipulation in a register containing a write-only bit example 3: bclr instruction executed de signating port 5 control register pcr5 p57 and p56 are input pins, with a low-level signal input at p57 and a high-level signal input at p56. p55 to p50 are output pins that output low-level signals. an example of setting the p50 pin as
section 2 cpu rev.5.00 nov. 02, 2005 page 47 of 418 rej09b0028-0500 an input pin by the bclr instruction is shown below. it is assumed that a high-level signal will be input to this input pin. ? p57 p56 p55 p54 p53 p52 p51 p50 input/output input input output output output output output output pin state low level high level low level low level low level low level low level low level pcr5 0 0 1 1 1 1 1 1 pdr5 1 0 0 0 0 0 0 0 ? bclr #0, @pcr5 the bclr instruction is executed for pcr5. ? p57 p56 p55 p54 p53 p52 p51 p50 input/output output output output output output ou tput output input pin state low level high level low level low level low level low level low level high level pcr5 1 1 1 1 1 1 1 0 pdr5 1 0 0 0 0 0 0 0 ?
section 2 cpu rev.5.00 nov. 02, 2005 page 48 of 418 rej09b0028-0500 ? prior to executing bclr instruction mov.b #3f, r0l mov.b r0l, @ram0 mov.b r0l, @pcr5 the pcr5 value (h'3f) is written to a work area in memory (ram0) as well as to pcr5. p57 p56 p55 p54 p53 p52 p51 p50 input/output input input output output output output output output pin state low level high level low level low level low level low level low level low level pcr5 0 0 1 1 1 1 1 1 pdr5 1 0 0 0 0 0 0 0 ram0 0 0 1 1 1 1 1 1 ? bclr instruction executed bclr #0, @ram0 the bclr instructions executed for the pcr5 work area (ram0). ? after executing bclr instruction mov.b @ram0, r0l mov.b r0l, @pcr5 the work area (ram0) value is written to pcr5. p57 p56 p55 p54 p53 p52 p51 p50 input/output input input output output output out put output output pin state low level high level low level low level low level low level low level high level pcr5 0 0 1 1 1 1 1 0 pdr5 1 0 0 0 0 0 0 0 ram0 0 0 1 1 1 1 1 0
section 3 exception handling rev.5.00 nov. 02, 2005 page 49 of 418 rej09b0028-0500 section 3 exception handling exception handling may be caused by a reset, a trap instruction (trapa), or interrupts. ? res pin. the chip is also reset when the watchdog timer overflows, and exception handling starts. exception handling is the same as exception handling by the res pin. ? ? 3.1 exception sources and vector address table 3.1 shows the vector addresses and priority of each exception handling. when more than one interrupt is requested, handling is performed from the interrupt with the highest priority. table 3.1 exception sou rces and vector address relative module exception sources vector number vector address priority res pin watchdog timer reset 0 h'0000 to h'0001 high ? reserved for system use 1 to 6 h'0002 to h'000d external interrupt pin nmi 7 h'000e to h'000f cpu trap instruction (#0) 8 h'0010 to h'0011 (#1) 9 h'0012 to h'0013 (#2) 10 h'0014 to h'0015 (#3) 11 h'0016 to h'0017 address break break conditions satisfied 12 h'0018 to h'0019 low
section 3 exception handling rev.5.00 nov. 02, 2005 page 50 of 418 rej09b0028-0500 relative module exception sources vector number vector address priority cpu direct transition by executing the sleep instruction 13 h'001a to h'001b high external interrupt pin irq0 low-voltage detection interrupt * 14 h'001c to h'001d irq1 15 h'001e to h'001f irq2 16 h'0020 to h'0021 irq3 17 h'0022 to h'0023 wkp 18 h'0024 to h'0025 timer a overflow 19 h?0026 to h?0027 ? reserved for system use 20 h?0028 to h?0029 timer w timer w input capture a /compare match a timer w input capture b /compare match b timer w input capture c /compare match c timer w input capture d /compare match d timer w overflow 21 h?002a to h?002b timer v timer v compare match a timer v compare match b timer v overflow 22 h'002c to h'002d sci3 sci3 receive data full sci3 transmit data empty sci3 transmit end sci3 receive error 23 h'002e to h'002f iic2 transmit data empty transmit end receive data full arbitration lost/overrun error nack detection stop conditions detected 24 h'0030 to h'0031 a/d converter a/d conversion end 25 h'0032 to h'0033 low note * a low-voltage detection interrupt is enabled only in the product with an on-chip power- on reset and low-voltage detection circuit.
section 3 exception handling rev.5.00 nov. 02, 2005 page 51 of 418 rej09b0028-0500 3.2 register descriptions interrupts are controlled by the following registers. ? interrupt edge select register 1 (iegr1) ? interrupt edge select register 2 (iegr2) ? interrupt enable register 1 (ienr1) ? interrupt flag register 1 (irr1) ? wakeup interrupt flag register (iwpr) 3.2.1 interrupt edge se lect register 1 (iegr1) iegr1 selects the direction of an edge that generates interrupt requests of pins nmi and irq3 to irq0 . bit bit name initial value r/w description 7 nmieg 0 r/w nmi edge select 0: falling edge of nmi pin input is detected 1: rising edge of nmi pin input is detected 6 to 4 ? all 1 ? reserved these bits are always read as 1. 3 ieg3 0 r/w irq3 edge select 0: falling edge of irq3 pin input is detected 1: rising edge of irq3 pin input is detected 2 ieg2 0 r/w irq2 edge select 0: falling edge of irq2 pin input is detected 1: rising edge of irq2 pin input is detected 1 ieg1 0 r/w irq1 edge select 0: falling edge of irq1 pin input is detected 1: rising edge of irq1 pin input is detected 0 ieg0 0 r/w irq0 edge select 0: falling edge of irq0 pin input is detected 1: rising edge of irq0 pin input is detected
section 3 exception handling rev.5.00 nov. 02, 2005 page 52 of 418 rej09b0028-0500 3.2.2 interrupt edge se lect register 2 (iegr2) iegr2 selects the direction of an edge that generates interrupt requests of the pins adtrg and wkp5 to wkp0 . bit bit name initial value r/w description 7, 6 ? all 1 ? reserved these bits are always read as 1. 5 wpeg5 0 r/w wkp5 edge select 0: falling edge of wkp5 ( adtrg ) pin input is detected 1: rising edge of wkp5 ( adtrg ) pin input is detected 4 wpeg4 0 r/w wkp4 edge select 0: falling edge of wkp4 pin input is detected 1: rising edge of wkp4 pin input is detected 3 wpeg3 0 r/w wkp3 edge select 0: falling edge of wkp3 pin input is detected 1: rising edge of wkp3 pin input is detected 2 wpeg2 0 r/w wkp2 edge select 0: falling edge of wkp2 pin input is detected 1: rising edge of wkp2 pin input is detected 1 wpeg1 0 r/w wkp1edge select 0: falling edge of wkp1 pin input is detected 1: rising edge of wkp1 pin input is detected 0 wpeg0 0 r/w wkp0 edge select 0: falling edge of wkp0 pin input is detected 1: rising edge of wkp0 pin input is detected
section 3 exception handling rev.5.00 nov. 02, 2005 page 53 of 418 rej09b0028-0500 3.2.3 interrupt enable register 1 (ienr1) ienr1 enables direct transition inte rrupts, timer a overflow interrupts, and external pin interrupts. bit bit name initial value r/w description 7 iendt 0 r/w direct transfer interrupt enable when this bit is set to 1, direct transition interrupt requests are enabled. 6 ienta 0 r/w timer a interrupt enable when this bit is set to 1, timer a overflow interrupt requests are enabled. 5 ienwp 0 r/w wakeup interrupt enable this bit is an enable bit, which is common to the pins wkp5 to wkp0 . when the bit is set to 1, interrupt requests are enabled. 4 ? 1 ? reserved this bit is always read as 1. 3 ien3 0 r/w irq3 interrupt enable when this bit is set to 1, interrupt requests of the irq3 pin are enabled. 2 ien2 0 r/w irq2 interrupt enable when this bit is set to 1, interrupt requests of the irq2 pin are enabled. 1 ien1 0 r/w irq1 interrupt enable when this bit is set to 1, interrupt requests of the irq1 pin are enabled. 0 ien0 0 r/w irq0 interrupt enable when this bit is set to 1, interrupt requests of the irq0 pin are enabled. when disabling interrupts by clearing bits in an in terrupt enable register, or when clearing bits in an interrupt flag register, always do so while interrupts are masked (i = 1). if the above clear operations are performed while i = 0, and as a resu lt a conflict arises between the clear instruction and an interrupt request, exception handling for the interrupt will be executed after the clear instruction has been executed.
section 3 exception handling rev.5.00 nov. 02, 2005 page 54 of 418 rej09b0028-0500 3.2.4 interrupt flag register 1 (irr1) irr1 is a status flag register for direct tran sition interrupts, timer a overflow interrupts, and irq3 to irq0 interrupt requests. bit bit name initial value r/w description 7 irrdt 0 r/w direct transfer interrupt request flag [setting condition] when a direct transfer is made by executing a sleep instruction while dton in syscr2 is set to 1. [clearing condition] when irrdt is cleared by writing 0 6 irrta 0 r/w timer a interrupt request flag [setting condition] when the timer a counter value overflows [clearing condition] when irrta is cleared by writing 0 5, 4 ? all 1 ? reserved these bits are always read as 1. 3 irri3 0 r/w irq3 interrupt request flag [setting condition] when irq3 pin is designated for interrupt input and the designated signal edge is detected. [clearing condition] when irri3 is cleared by writing 0 2 irri2 0 r/w irq2 interrupt request flag [setting condition] when irq2 pin is designated for interrupt input and the designated signal edge is detected. [clearing condition] when irri2 is cleared by writing 0 1 irri1 0 r/w irq1 interrupt request flag [setting condition] when irq1 pin is designated for interrupt input and the designated signal edge is detected. [clearing condition] when irri1 is cleared by writing 0
section 3 exception handling rev.5.00 nov. 02, 2005 page 55 of 418 rej09b0028-0500 bit bit name initial value r/w description 0 irrl0 0 r/w irq0 interrupt request flag [setting condition] when irq0 pin is designated for interrupt input and the designated signal edge is detected. [clearing condition] when irri0 is cleared by writing 0 3.2.5 wakeup interrupt flag register (iwpr) iwpr is a status flag register for wkp5 to wkp0 interrupt requests. bit bit name initial value r/w description 7, 6 ? all 1 ? reserved these bits are always read as 1. 5 iwpf5 0 r/w wkp5 interrupt request flag [setting condition] when wkp5 pin is designated for interrupt input and the designated signal edge is detected. [clearing condition] when iwpf5 is cleared by writing 0. 4 iwpf4 0 r/w wkp4 interrupt request flag [setting condition] when wkp4 pin is designated for interrupt input and the designated signal edge is detected. [clearing condition] when iwpf4 is cleared by writing 0. 3 iwpf3 0 r/w wkp3 interrupt request flag [setting condition] when wkp3 pin is designated for interrupt input and the designated signal edge is detected. [clearing condition] when iwpf3 is cleared by writing 0.
section 3 exception handling rev.5.00 nov. 02, 2005 page 56 of 418 rej09b0028-0500 bit bit name initial value r/w description 2 iwpf2 0 r/w wkp2 interrupt request flag [setting condition] when wkp2 pin is designated for interrupt input and the designated signal edge is detected. [clearing condition] when iwpf2 is cleared by writing 0. 1 iwpf1 0 r/w wkp1 interrupt request flag [setting condition] when wkp1 pin is designated for interrupt input and the designated signal edge is detected. [clearing condition] when iwpf1 is cleared by writing 0. 0 iwpf0 0 r/w wkp0 interrupt request flag [setting condition] when wkp0 pin is designated for interrupt input and the designated signal edge is detected. [clearing condition] when iwpf0 is cleared by writing 0. 3.3 reset exception handling when the res pin goes low, all processing halts and this lsi enters the reset. the internal state of the cpu and the registers of the on-chip peripheral modules are initialized by the reset. to ensure that this lsi is reset at power-up, hold the res pin low until the clock pulse generator output stabilizes. to reset the chip during operation, hold the res pin low for at least 10 system clock cycles. when the res pin goes high after bei ng held low for the necessary time, this lsi starts reset exception handling. the reset exception handling sequence is shown in figure 3.1. the reset exception handling sequence is as follows. however, for the reset exception handling sequence of the product with on-chip power-on reset circuit, refer to section 18, power-on reset and low-voltage detecti on circuits (optional). 1. set the i bit in the condition code register (ccr) to 1. 2. the cpu generates a reset exception handling vector address (from h'0000 to h'0001), the data in that address is sent to the program counter (pc) as the start address, and program execution starts from that address.
section 3 exception handling rev.5.00 nov. 02, 2005 page 57 of 418 rej09b0028-0500 3.4 interrupt exception handling 3.4.1 external interrupts as the external interrupts, there are nmi, ir q3 to irq0, and wkp5 to wkp0 interrupts. nmi interrupt nmi interrupt is requested by input signal edge to pin nmi . this interrupt is detected by either rising edge sensing or falling edge sensing, depending on the setting of bit nmieg in iegr1. nmi is the highest-priority interrupt, and can always be accepted without depending on the i bit value in ccr. irq3 to irq0 interrupts irq3 to irq0 interrupts are requested by input signals to pins irq3 to irq0 . these four interrupts are given different vect or addresses, and are detected individually by either rising edge sensing or falling edge sensing, depending on the settings of bits ieg3 to ieg0 in iegr1. when pins irq3 to irq0 are designated for interrupt input in pmr1 and the designated signal edge is input, the corresponding bit in irr1 is set to 1, requesting the cpu of an interrupt. these interrupts can be masked by setting bits ien3 to ien0 in ienr1. wkp5 to wkp0 interrupts wkp5 to wkp0 interrupts are requested by input signals to pins wkp 5 to wkp 0. these six interrupts have the same vector addresses, and are detected individually by either rising edge sensing or falling edge sensing, depending on the settings of bits wpeg5 to wpeg0 in iegr2. when pins wkp5 to wkp0 are designated for interrupt input in pmr5 and the designated signal edge is input, the corresponding bit in iwpr is set to 1, requesting the cpu of an interrupt. these interrupts can be mask ed by setting bit ienwp in ienr1.
section 3 exception handling rev.5.00 nov. 02, 2005 page 58 of 418 rej09b0028-0500 vector fetch internal address bus internal read signal internal write signal internal data bus (16 bits) res internal processing initial program instruction prefetch (1) reset exception handling vector address (h'0000) (2) program start address (3) initial program instruction (2) (3) (2) (1) reset cleared figure 3.1 reset sequence 3.4.2 internal interrupts each on-chip peripheral module has a flag to show the interrupt request status and the enable bit to enable or disable the interrupt. for timer a interrupt requests and direct transfer interrupt requests generated by execution of a sleep instruction, th is function is included in irr1 and ienr1. when an on-chip peripheral module requests an interrupt, the corresponding interrupt request status flag is set to 1, requesting the cpu of an interrupt. these interrupts can be masked by writing 0 to clear the corresponding enable bit. 3.4.3 interrupt handling sequence interrupts are controlled by an interrupt controller. interrupt operation is described as follows. 1. if an interrupt occurs while the nmi or interrupt enable bit is set to 1, an interrupt request signal is sent to the interrupt controller.
section 3 exception handling rev.5.00 nov. 02, 2005 page 59 of 418 rej09b0028-0500 2. when multiple interrupt requests are generated, the interrupt controller requests to the cpu for the interrupt handling with the highest priority at that time according to table 3.1. other interrupt requests are held pending. 3. the cpu accepts the nmi and address break wi thout depending on the i bit value. other interrupt requests are accepted, if the i bit is clear ed to 0 in ccr; if the i bit is set to 1, the interrupt request is held pending. 4. if the cpu accepts the interrupt after proces sing of the current instruction is completed, interrupt exception handling will begin. first, both pc and ccr are pushed onto the stack. the state of the stack at this time is shown in figure 3.2. the pc value pushed onto the stack is the address of the first instruction to be exec uted upon return from interrupt handling. 5. then, the i bit of ccr is set to 1, masking further interrupts excluding the nmi and address break. upon return from interrupt handling, the values of i bit and other bits in ccr will be restored and returned to the values prior to the start of interrupt exception handling. 6. next, the cpu generates the vector addres s corresponding to th e accepted interrupt, and transfers the address to pc as a start address of the interr upt handling-routine. then a program starts executing from the address indicated in pc. figure 3.3 shows a typical interrupt sequence where the program area is in the on-chip rom and the stack area is in the on-chip ram.
section 3 exception handling rev.5.00 nov. 02, 2005 page 60 of 418 rej09b0028-0500 pc and ccr saved to stack sp (r7) sp ? 1 sp ? 2 sp ? 3 sp ? 4 stack area sp + 4 sp + 3 sp + 2 sp + 1 sp (r7) even address prior to start of interrupt exception handling after completion of interrupt exception handling [legend] pc h : pc l : ccr: sp: upper 8 bits of program counter (pc) lower 8 bits of program counter (pc) condition code register stack pointer notes: ccr ccr * 3 pch pcl 1. 2. pc shows the address of the first instruction to be executed upon return from the interrupt handling routine. register contents must always be saved and restored by word length, starting from an even-numbered address. 3. ignored when returning from the interrupt handling routine. figure 3.2 stack status after exception handling 3.4.4 interrupt response time table 3.2 shows the number of wait states after an interrupt request flag is set until the first instruction of the interrupt handling-routine is executed. table 3.2 interrupt wait states item states total waiting time for completion of executing instruction * 1 to 23 15 to 37 saving of pc and ccr to stack 4 vector fetch 2 instruction fetch 4 internal processing 4 note: * not including eepmov instruction.
section 3 exception handling rev.5.00 nov. 02, 2005 page 61 of 418 rej09b0028-0500 vector fetch internal address bus internal read signal internal write signal (2) internal data bus (16 bits) interrupt request signal (9) (1) internal processing prefetch instruction of interrupt-handling routine (1) instruction prefetch address (instruction is not executed. address is saved as pc contents, becoming return address.) (2)(4) instruction code (not executed) (3) instruction prefetch address (instruction is not executed.) (5) sp ? 2 (6) sp ? 4 (7) ccr (8) vector address (9) starting address of interrupt-handling routine (contents of vector) (10) first instruction of interrupt-handling routine (3) (9) (8) (6) (5) (4) (1) (7) (10) stack access internal processing instruction prefetch interrupt level decision and wait for end of instruction interrupt is accepted figure 3.3 interrupt sequence
section 3 exception handling rev.5.00 nov. 02, 2005 page 62 of 418 rej09b0028-0500 3.5 usage notes 3.5.1 interrupts after reset if an interrupt is accepted after a reset and before the stack pointer (sp) is initialized, the pc and ccr will not be saved correctly, leading to a program crash. to prevent this, all interrupt requests, including nmi, are disabled immediately after a re set. since the first instruction of a program is always executed immediatel y after the reset state ends, make sure that this instruction initializes the stack pointer (example: mov.w #xx: 16, sp). 3.5.2 notes on stack area use when word data is accessed, the l east significant bit of the address is regarded as 0. access to the stack always takes place in word size, so the st ack pointer (sp: r7) shoul d never indicate an odd address. use push rn (mov.w rn, @?sp) or po p rn (mov.w @sp+, rn) to save or restore register values. 3.5.3 notes on rewriting port mode registers when a port mode register is rewritten to swit ch the functions of external interrupt pins, irq3 to irq0 , and wkp5 to wkp0 , the interrupt request flag may be set to 1. when switching a pin function, mask the interrupt before setting the bit in the port mode register. after accessing the port mode register, execute at l east one instruction (e.g., nop), then clear the interrupt request flag from 1 to 0. figure 3.4 shows a port mode register setting and interrupt request flag clearing procedure. ccr i bit 1 set port mode register bit execute nop instruction interrupts masked. (another possibility is to disable the relevant interrupt in interrupt enable register 1.) after setting the port mode register bit, first execute at least one instruction (e.g., nop), then clear the interrupt request flag to 0. interrupt mask cleared clear interrupt request flag to 0 ccr i bit 0 figure 3.4 port mode register setting and interrupt request flag clearing procedure
section 4 address break abk0001a_000020020200 rev.5.00 nov. 02, 2005 page 63 of 418 rej09b0028-0500 section 4 address break the address break simplifies on-board program debugg ing. it requests an address break interrupt when the set break condition is satisfied. the interr upt request is not affected by the i bit of ccr. break conditions that can be set include instruction execution at a specific address and a combination of access and data at a specific addr ess. with the address break function, the execution start point of a program containing a bug is detected and execution is branched to the correcting program. figure 4.1 shows a block diagram of the address break. barh barl bdrh bdrl abrkcr abrksr internal address bus comparator interrupt generation control circuit internal data bus comparator interrupt [legend] barh, barl: break address register bdrh, bdrl: break data register abrkcr: address break control register abrksr: address break status register figure 4.1 block diagram of address break 4.1 register descriptions address break has the following registers. ? ? ? ?
section 4 address break rev.5.00 nov. 02, 2005 page 64 of 418 rej09b0028-0500 4.1.1 address break control register (abrkcr) abrkcr sets address break conditions. bit bit name initial value r/w description 7 rtinte 1 r/w rte interrupt enable when this bit is 0, the interrupt immediately after executing rte is masked a nd then one instruction must be executed. when this bit is 1, the interrupt is not masked. 6 5 csel1 csel0 0 0 r/w r/w condition select 1 and 0 these bits set address break conditions. 00: instruction execution cycle 01: cpu data read cycle 10: cpu data write cycle 11: cpu data read/write cycle 4 3 2 acmp2 acmp1 acmp0 0 0 0 r/w r/w r/w address compare condition select 2 to 0 these bits set the comparison condition between the address set in bar and the internal address bus. 000: compares 16-bit addresses 001: compares upper 12-bit addresses 010: compares upper 8-bit addresses 011: compares upper 4-bit addresses 1xx: reserved (setting prohibited) 1 0 dcmp1 dcmp0 0 0 r/w r/w data compare condition select 1 and 0 these bits set the comparison condition between the data set in bdr and the internal data bus. 00: no data comparison 01: compares lower 8-bit data between bdrl and data bus 10: compares upper 8-bit data between bdrh and data bus 11: compares 16-bit data between bdr and data bus legend: x: don't care.
section 4 address break rev.5.00 nov. 02, 2005 page 65 of 418 rej09b0028-0500 when an address break is set in the data read cy cle or data write cycle, the data bus used will depend on the combination of the byte/word access and address. table 4.1 shows the access and data bus used. when an i/o register space with an 8-bit data bus width is accessed in word size, a byte access is generated twice. for details on da ta widths of each regi ster, see section 20.1, register addresses (address order). table 4.1 access and data bus used word access byte access even address odd address even address odd address rom space upper 8 bits lower 8 bits upper 8 bits upper 8 bits ram space upper 8 bits lower 8 bits upper 8 bits upper 8 bits i/o register with 8-bit data bus width upper 8 bits upper 8 bits upper 8 bits upper 8 bits i/o register with 16-bit data bus width upper 8 bits lower 8 bits ? ? 4.1.2 address break status register (abrksr) abrksr consists of the address break interrupt flag and the address break interrupt enable bit. bit bit name initial value r/w description 7 abif 0 r/w address break interrupt flag [setting condition] when the condition set in abrkcr is satisfied [clearing condition] when 0 is written after abif=1 is read 6 abie 0 r/w address break interrupt enable when this bit is 1, an address break interrupt request is enabled. 5 to 0 ? all 1 ? reserved these bits are always read as 1.
section 4 address break rev.5.00 nov. 02, 2005 page 66 of 418 rej09b0028-0500 4.1.3 break address re gisters (barh, barl) barh and barl are 16-bit read/w rite registers that set the address for generating an address break interrupt. when setting the address break condition to the instruction execution cycle, set the first byte address of the instruction. th e initial value of this register is h'ffff. 4.1.4 break data registers (bdrh, bdrl) bdrh and bdrl are 16-bit read/w rite registers that set the data for generating an address break interrupt. bdrh is compared with the upper 8-bit data bus. bdrl is compared with the lower 8- bit data bus. when memory or registers are accessed by byte, the u pper 8-bit data bus is used for even and odd addresses in the data transmission. therefore, comparison data must be set in bdrh for byte access. fo r word access, the data bus used depe nds on the address. see section 4.1.1, address break control register (abrkcr), for details. the initial value of this register is undefined. 4.2 operation when the abif and abie bits in abrksr are set to 1, the address break function generates an interrupt request to the cpu. the abif bit in abrksr is set to 1 by the combination of the address set in bar, the data set in bdr, and th e conditions set in abrkcr. when the interrupt request is accepted, interr upt exception handling starts after the instruction being executed ends. the address break interrupt is not masked by the i bit in ccr of the cpu.
section 4 address break rev.5.00 nov. 02, 2005 page 67 of 418 rej09b0028-0500 figures 4.2 show the operation examples of the address break interrupt setting. nop instruc- tion prefetch register setting abrkcr = h'80 bar = h'025a program 0258 025a 025c 0260 0262 : * nop nop mov.w @h'025a,r0 nop nop : 0258 address bus interrupt request 025a 025c 025e sp-2 sp-4 nop instruc- tion prefetch mov instruc- tion 1 prefetch mov instruc- tion 2 prefetch internal processing stack save interrupt acceptance underline indicates the address to be stacked. when the address break is specified in instruction execution cycle figure 4.2 address break in terrupt operation example (1) mov instruc- tion 1 prefetch register setting abrkcr = h'a0 bar = h'025a program 0258 025a 025c 0260 0262 : * nop nop mov.w @h'025a,r0 nop nop : 025c address bus interrupt request 025e 0260 025a 0262 0264 sp-2 mov instruc- tion 2 prefetch nop instruc- tion prefetch mov instruc- tion execution next instru- ction prefetch internal processing stack save nop instruc- tion prefetch interrupt acceptance underline indicates the address to be stacked. when the address break is specified in the data read cycle figure 4.2 address break in terrupt operation example (2)
section 4 address break rev.5.00 nov. 02, 2005 page 68 of 418 rej09b0028-0500
section 5 clock pulse generators cpg0200a_000020020200 rev.5.00 nov. 02, 2005 page 69 of 418 rej09b0028-0500 section 5 clock pulse generators clock oscillator circuitry (cpg: clock pulse generator) is provided on-chip, including both a system clock pulse generator and a subclock puls e generator. the system clock pulse generator consists of a system clock oscillator, a duty co rrection circuit, and system clock dividers. the subclock pulse generator consists of a subclock oscillator circuit and a subclock divider. figure 5.1 shows a block diagram of the clock pulse generators. system clock oscillator subclock oscillator subclock divider duty correction circuit system clock divider prescaler s (13 bits) prescaler w (5 bits) osc 1 osc 2 x 1 x 2 system clock pulse generator osc (f osc ) osc (f osc ) w (f w ) w /2 w /4 sub /2 to /8192 w /8 osc /8 osc osc /16 osc /32 osc /64 w /8 to w /128 subclock pulse generator figure 5.1 block diagram of clock pulse generators the basic clock signals that drive the cpu and on-chip peripheral modules are
section 5 clock pulse generators rev.5.00 nov. 02, 2005 page 70 of 418 rej09b0028-0500 5.1 system clock generator clock pulses can be supplied to the system clock divider either by connecting a crystal or ceramic resonator, or by providing external clock input. figure 5.2 shows a block diagram of the system clock generator. lpm lpm: low-power mode (standby mode, subactive mode, subsleep mode) 2 1 osc osc figure 5.2 block diagram of system clock generator 5.1.1 connecting crystal resonator figure 5.3 shows a typical method of connecting a crystal resonator. an at-cut parallel-resonance crystal resonator should be used. figure 5.4 shows the equivalent circuit of a crystal resonator. a resonator having the characteristics given in table 5.1 should be used. 1 2 c 1 c 2 osc osc c = c = 10 to 22 pf 12 figure 5.3 typical connect ion to crystal resonator c s c 0 r s osc 1 osc 2 l s figure 5.4 equivalent circuit of crystal resonator
section 5 clock pulse generators rev.5.00 nov. 02, 2005 page 71 of 418 rej09b0028-0500 table 5.1 crystal resonator parameters frequency (mhz) 2 4 8 10 16 20 r s (max) 500 ? 120 ? 80 ? 60 ? 50 ? 40 ? c 0 (max) 7 pf 7 pf 7 pf 7 pf 7 pf 7 pf 5.1.2 connecting ceramic resonator figure 5.5 shows a typical method of connecting a ceramic resonator. osc 1 osc 2 c 1 c 2 c 1 = 5 to 30 pf c 2 = 5 to 30 pf figure 5.5 typical connect ion to cerami c resonator 5.1.3 external clock input method connect an external clock signal to pin osc 1 , and leave pin osc 2 open. figure 5.6 shows a typical connection. the duty cycle of the external clock sign al must be 45 to 55%. osc 1 external clock input osc 2 open figure 5.6 example of external clock input
section 5 clock pulse generators rev.5.00 nov. 02, 2005 page 72 of 418 rej09b0028-0500 5.2 subclock generator figure 5.7 shows a block diagram of the subclock generator. note : registance is a reference value. 2 8m ? 1 x x figure 5.7 block diagram of subclock generator 5.2.1 connecting 32.768-khz crystal resonator clock pulses can be supplied to the subclock divider by connecting a 32.768-khz crystal resonator, as shown in figure 5.8. figure 5.9 shows the equivalent circuit of the 32.768-khz crystal resonator. x x c 1 c 2 1 2 c = c = 15 pf (typ.) 12 figure 5.8 typical connection to 32.768-khz crystal resonator x 1 x 2 l s c s c o c o = 1.5 pf (typ.) r s = 14 k ? (typ.) f w = 32.768 khz r s note: constants are reference values. figure 5.9 equivalent circuit of 32.768-khz crystal resonator
section 5 clock pulse generators rev.5.00 nov. 02, 2005 page 73 of 418 rej09b0028-0500 5.2.2 pin connection when not using subclock when the subclock is not used, connect pin x 1 to v cl or v ss and leave pin x 2 open, as shown in figure 5.10. x 1 v cl or v ss x 2 open figure 5.10 pin connection when not using subclock 5.3 prescalers 5.3.1 prescaler s prescaler s is a 13-bit counter using the system clock ( ) as its input clock. it is incremented once per clock period. prescaler s is initialized to h'0000 by a reset, and starts counting on exit from the reset state. in standby mo de, subactive mode, and subsleep mode, the system clock pulse generator stops. prescaler s also stops and is ini tialized to h'0000. the cp u cannot read or write prescaler s. the output from pres caler s is shared by the on-chi p peripheral modules. the divider ratio can be set separately for each on-chip peri pheral function. in activ e mode and sleep mode, the clock input to prescaler s is determined by the division factor designated by ma2 to ma0 in syscr2. 5.3.2 prescaler w prescaler w is a 5-bit counter using a 32.768 khz signal divided by 4 ( w /4) as its input clock. the divided output is used for clock time base operation of timer a. prescaler w is initialized to h'00 by a reset, and starts counting on exit from the re set state. even in stan dby mode, subactive mode, or subsleep mode, prescaler w continues functioning so long as clock signals are supplied to pins x 1 and x 2 . prescaler w can be reset by setting 1s in bits tma3 and tma2 of timer mode register a (tma).
section 5 clock pulse generators rev.5.00 nov. 02, 2005 page 74 of 418 rej09b0028-0500 5.4 usage notes 5.4.1 note on resonators resonator characteristics are closely related to boar d design and should be carefully evaluated by the user, referring to the examples shown in this section. resonator circuit constants will differ depending on the resonator element, stray capac itance in its interconnecting circuit, and other factors. suitable constants should be determined in consultation with the resonator element manufacturer. design the circuit so that the resonator element never receives voltages exceeding its maximum rating. 5.4.2 notes on board design when using a crystal resonator (ceramic resonator) , place the resonator and it s load capacitors as close as possible to the osc 1 and osc 2 pins. other signal lines should be routed away from the resonator circuit to prevent induc tion from interfering with correct oscillation (see figure 5.11). osc 1 osc 2 c 1 c 2 signal a signal b avoid figure 5.11 example of incorrect board design
section 6 power-down modes lpw3003a_000020020200 rev.5.00 nov. 02, 2005 page 75 of 418 rej09b0028-0500 section 6 power-down modes this lsi has six modes of operation after a reset. these include a normal active mode and four power-down modes, in which power consumption is significantly reduced. module standby mode reduces power consumption by selectively halting on-chip module functions. ? ? ? ? ? ? 6.1 register descriptions the registers related to power-down modes are listed below. ? ? ?
section 6 power-down modes rev.5.00 nov. 02, 2005 page 76 of 418 rej09b0028-0500 6.1.1 system control register 1 (syscr1) syscr1 controls the power-down modes, as well as syscr2. bit bit name initial value r/w description 7 ssby 0 r/w software standby this bit selects the mode to tr ansit after the execution of the sleep instruction. 0: a transition is made to sleep mode or subsleep mode. 1: a transition is made to standby mode. for details, see table 6.2. 6 5 4 sts2 sts1 sts0 0 0 0 r/w r/w r/w standby timer select 2 to 0 these bits designate the time the cpu and peripheral modules wait for stable clock operation after exiting from standby mode, subactive mode, or subsleep mode to active mode or sleep mode due to an interrupt. the designation should be made according to the clock frequency so that the waiting time is at least 6.5 ms. the relationship between the specified value and the number of wait states is shown in table 6.1. when an external clock is to be used, the minimum value (sts2 = sts1 = sts0 = 1) is recommended. 3 nesel 0 r/w noise eliminat ion sampling frequency select the subclock pulse generator generates the watch clock signal ( w ) and the system clock pulse generator generates the oscillator clock ( osc ). this bit selects the sampling frequency of the oscillator clock when the watch clock signal ( w ) is sampled. when osc = 4 to 20 mhz, clear nesel to 0. 0: sampling rate is osc /16 1: sampling rate is osc /4 2 to 0 ? all 0 ? reserved these bits are always read as 0.
section 6 power-down modes rev.5.00 nov. 02, 2005 page 77 of 418 rej09b0028-0500 table 6.1 operating frequency and waiting time sts2 sts1 sts0 waiting time 20 mhz 16 mhz 10 mhz 8 mhz 4 mhz 2 mhz 1 mhz 0.5 mhz 0 0 0 8,192 states 0.4 0.5 0.8 1.0 2.0 4.1 8.1 16.4 1 16,384 states 0.8 1.0 1.6 2.0 4.1 8.2 16.4 32.8 1 0 32,768 states 1.6 2.0 3.3 4.1 8.2 16.4 32.8 65.5 1 65,536 states 3.3 4.1 6.6 8.2 16.4 32.8 65.5 131.1 1 0 0 131,072 states 6.6 8.2 13.1 16.4 32.8 65.5 131.1 262.1 1 1,024 states 0.05 0.06 0.10 0.13 0.26 0.51 1.02 2.05 1 0 128 states 0.00 0.00 0.01 0.02 0.03 0.06 0.13 0.26 1 16 states 0.00 0.00 0.00 0.00 0.00 0.01 0.02 0.03 note: time unit is ms.
section 6 power-down modes rev.5.00 nov. 02, 2005 page 78 of 418 rej09b0028-0500 6.1.2 system control register 2 (syscr2) syscr2 controls the power-down modes, as well as syscr1. bit bit name initial value r/w description 7 6 5 smsel lson dton 0 0 0 r/w r/w r/w sleep mode selection low speed on flag direct transfer on flag these bits select the mode to transit after the execution of a sleep instruction, as well as bit ssby of syscr1. for details, see table 6.2. 4 3 2 ma2 ma1 ma0 0 0 0 r/w r/w r/w active mode clock select 2 to 0 these bits select the operating clock frequency in active and sleep modes. the operating clock frequency changes to the set frequency after the sleep instruction is executed. 0xx: osc 100: osc /8 101: osc /16 110: osc /32 111: osc /64 1 0 sa1 sa0 0 0 r/w r/w subactive mode clock select 1 and 0 these bits select the operating clock frequency in subactive and subsleep modes. the operating clock frequency changes to the set frequency after the sleep instruction is executed. 00: w /8 01: w /4 1x: w /2 legend: x : don't care.
section 6 power-down modes rev.5.00 nov. 02, 2005 page 79 of 418 rej09b0028-0500 6.1.3 module standby control register 1 (mstcr1) mstcr1 allows the on-chip peripheral module s to enter a standby state in module units. bit bit name initial value r/w description 7 ? 0 ? reserved this bit is always read as 0. 6 mstiic 0 r/w iic module standby iic enters standby mode when this bit is set to 1 5 msts3 0 r/w sci3 module standby sci3 enters standby mode when this bit is set to 1 4 mstad 0 r/w a/d converter module standby a/d converter enters standby mode when this bit is set to 1 3 mstwd 0 r/w watchdog timer module standby watchdog timer enters standby mode when this bit is set to 1.when the internal oscillator is selected for the watchdog timer clock, the watchdog timer operates regardless of the setting of this bit 2 msttw 0 r/w timer w module standby timer w enters standby mode when this bit is set to 1 1 msttv 0 r/w timer v module standby timer v enters standby mode when this bit is set to 1 0 mstta 0 r/w timer a module standby timer a enters standby mode when this bit is set to 1
section 6 power-down modes rev.5.00 nov. 02, 2005 page 80 of 418 rej09b0028-0500 6.2 mode transitions and states of lsi figure 6.1 shows the possible transitions among these operating modes. a transition is made from the program execution state to the program halt state of the program by executing a sleep instruction. interrupts allow for returning from the program halt state to the program execution state of the program. a direct transition between active mode and subactive mode, which are both program execution states, can be made without halting the program. the operating frequency can also be changed in the same modes by making a transition directly from active mode to active mode, and from subactive mode to subactive mode. res input enables transitions from a mode to the reset state. table 6.2 shows the transition conditions of each mode after the sleep instruction is executed and a mode to return by an interrupt. table 6.3 shows the internal states of the lsi in each mode. reset state standby mode active mode sleep mode subsleep mode subactive mode program halt state program execution state program halt state sleep instruction sleep instruction interrupt direct transition interrupt direct transition interrupt notes: 1. to make a transition to another mode by an interrupt, make sure interrupt handling is after the interrupt is accepted. 2. details on the mode transition conditions are given in table 6.2. sleep instruction direct transition interrupt direct transition interrupt interrupt sleep instruction interrupt interrupt sleep instruction interrupt sleep instruction figure 6.1 mode transition diagram
section 6 power-down modes rev.5.00 nov. 02, 2005 page 81 of 418 rej09b0028-0500 table 6.2 transition mode after sleep inst ruction execution and interrupt handling dton ssby smsel lson transition mode after sleep instruction execution transition mode due to interrupt 0 0 0 0 sleep mode active mode 1 subactive mode 1 0 subsleep mode active mode 1 subactive mode 1 x x standby mode active mode 1 x 0 * 0 active mode (direct transition) ? x x 1 subactive mode (direct transition) ? legend: x : don?t care. * when a state transition is performed while smsel is 1, timer v, sci3, and the a/d converter are reset, and all registers are set to their initial values. to use these functions after entering active mode, reset the registers.
section 6 power-down modes rev.5.00 nov. 02, 2005 page 82 of 418 rej09b0028-0500 table 6.3 internal state in each operating mode function active mode sleep mode subactive mode subsleep mode standby mode system clock oscillator functioning functioning halted halted halted subclock oscillator functioning functi oning functioning functioning functioning instructions functioning halted functioning halted halted cpu operations registers functioning retained functioning retained retained ram functioning retained f unctioning retained retained io ports functioning retained functioning retained register contents are retained, but output is the high- impedance state. irq3 to irq0 functioning functioni ng functioning functioning functioning external interrupts wkp5 to wkp0 functioning functioning functi oning functioning functioning timer a functioning functioning functi oning if the timekeeping time-base function is selected, and retained if not selected timer v functioning functioning reset reset reset timer w functioning functioning retained (if internal clock is selected as a count clock, the counter is incremented by a subclock * ) retained watchdog timer functioning functioning retained (functioning if the internal oscillator is selected as a count clock * ) sci3 functioning functioning reset reset reset iic functioning functioning retained * retained retained peripheral functions a/d converter functioning functioning reset reset reset note: * registers can be read or written in subactive mode.
section 6 power-down modes rev.5.00 nov. 02, 2005 page 83 of 418 rej09b0028-0500 6.2.1 sleep mode in sleep mode, cpu operation is halted but the on-chip peripheral modules function at the clock frequency set by the ma2, ma1, and ma0 bits in syscr2. cpu register contents are retained. when an interrupt is requested, sleep mode is cleared and interrupt exception handling starts. sleep mode is not cleared if the i bit of the co ndition code register (ccr) is set to 1 or the requested interrupt is disabled in the interrupt enable register. after sleep mode is cleared, a transition is made to active mode when the lson bi t in syscr2 is 0, and a transition is made to subactive mode when the bit is 1. when the res pin goes low, the cpu goes into the reset state and sleep mode is cleared. 6.2.2 standby mode in standby mode, the clock pulse generator stops, so the cpu and on-chip peripheral modules stop functioning. however, as long as the rated voltage is supplied, the contents of cpu registers, on- chip ram, and some on-chip peripheral module registers are retained. on-chip ram contents will be retained as long as the voltage set by the ram data retention voltage is provided. the i/o ports go to the high-impedance state. standby mode is cleared by an in terrupt. when an interrupt is requested, the system clock pulse generator starts. after the time set in bits st s2?sts0 in syscr1 has elapsed, and interrupt exception handling starts. standby mode is not cleared if the i bit of ccr is set to 1 or the requested interrupt is disabled in the interrupt enable register. when the res pin goes low, the system clock pulse generator starts. since system clock signals are supplied to the entire ch ip as soon as the system clock puls e generator starts functioning, the res pin must be kept low until the pulse generator output stabilizes. after the pulse generator output has stabilized, the cpu starts reset exception handling if the res pin is driven high. 6.2.3 subsleep mode in subsleep mode, operation of the cpu and on-chip peripheral modules other than timer a is halted. as long as a required voltage is applied, the contents of cpu registers, the on-chip ram, and some registers of the on-chip peripheral modul es are retained. i/o ports keep the same states as before the transition. subsleep mode is cleared by an in terrupt. when an interrupt is requ ested, subsleep mode is cleared and interrupt exception handling starts. subsleep mode is not cleared if the i bit of ccr is set to 1 or the requested interrupt is disabled in the in terrupt enable register. after subsleep mode is
section 6 power-down modes rev.5.00 nov. 02, 2005 page 84 of 418 rej09b0028-0500 cleared, a transition is made to active mode when th e lson bit in syscr2 is 0, and a transition is made to subactive mode when the bit is 1. when the res pin goes low, the system clock pulse generator starts. since system clock signals are supplied to the entire chip as soon as the system clock pu lse generator starts functioning, the res pin must be kept low until the pulse generator output stabilizes. after the pulse generator output has stabilized, the cpu starts reset exception handling if the res pin is driven high. 6.2.4 subactive mode the operating frequency of subactive mode is selected from res pin goes low, the system clock pulse generator starts. since system clock signals are supplied to the entire chip as soon as the system clock pulse generator starts functioning, the res pin must be kept low until the pulse generator output stabilizes. after the pulse generator output has stabilized, the cpu starts reset exception handling if the res pin is driven high. 6.3 operating frequency in active mode operation in active mode is clocked at the frequency designated by the ma2, ma1, and ma0 bits in syscr2. the operating frequency changes to the set frequency after sleep instruction execution.
section 6 power-down modes rev.5.00 nov. 02, 2005 page 85 of 418 rej09b0028-0500 6.4 direct transition the cpu can execute programs in two modes: activ e and subactive mode. a direct transition is a transition between these two modes without stoppi ng program execution. a direct transition can be made by executing a sleep instruction while the dton bit in syscr2 is set to 1. the direct transition also enables operating frequency modi fication in active or subactive mode. after the mode transition, direct transition interrupt exception handling starts. if the direct transition interrupt is disabled in in terrupt enable register 1, a transition is made instead to sleep or subsleep mode. note that if a direct transition is attempted while the i bit in ccr is set to 1, sleep or subsleep mode will be en tered, and the resulting mode cannot be cleared by means of an interrupt. 6.4.1 direct transition from ac tive mode to subactive mode the time from the start of sleep instruction execu tion to the end of interrupt exception handling (the direct transition time) is calculated by equation (1). direct transition time = {(number of sleep instru ction execution states) + (number of internal processing states)} (tcyc before transition) + (number of interrupt exception handling states) (tsubcyc after transition) (1) example direct transition time = (2 + 1) tosc + 14 8tw = 3tosc + 112tw (when the cpu operating clock of osc w /8 is selected) legend tosc: osc clock cycle time tw: watch clock cycle time tcyc: system clock ( ) cycle time tsubcyc: subclock ( sub ) cycle time 6.4.2 direct transition from su bactive mode to active mode the time from the start of sleep instruction execution to the end of interrupt exception handling (the direct transition time) is calculated by equation (2). direct transition time = {(number of sleep inst ruction execution states) + (number of internal processing states)} (tsubcyc before transition) + {(waiting time set in bits sts2 to sts0) + (number of interrupt exception handling states)} (tcyc after transition) (2)
section 6 power-down modes rev.5.00 nov. 02, 2005 page 86 of 418 rej09b0028-0500 example direct transition time = (2 + 1) 8tw + (8192 + 14) tosc = 24tw + 8206tosc (when the cpu operating clock of w /8 osc and a waiting time of 8192 states are selected) legend tosc: osc clock cycle time tw: watch clock cycle time tcyc: system clock ( ) cycle time tsubcyc: subclock ( sub ) cycle time 6.5 module standby function the module-standby function can be set to any peripheral module. in module standby mode, the clock supply to modules stops to enter the po wer-down mode. module standby mode enables each on-chip peripheral module to enter the standby st ate by setting a bit that corresponds to each module to 1 and cancels the mode by clearing the bit to 0.
section 7 rom rom3321a_000120030300 rev.5.00 nov. 02, 2005 page 87 of 418 rej09b0028-0500 section 7 rom the features of the 32-kbyte flash memory built into the flash memory version are summarized below. ? ? ? ? ? ? ? ? ? ? ? ? ? ? 7.1 block configuration figure 7.1 shows the block configuration of 32-kbyte flash memory. the thick lines indicate erasing units, the narrow lines indi cate programming units, and the va lues are addresses. the flash memory is divided into 1 kbyte
section 7 rom rev.5.00 nov. 02, 2005 page 88 of 418 rej09b0028-0500 h'007f h'0000 h'0001 h'0002 h'00ff h'0080 h'0081 h'0082 h'03ff h'0380 h'0381 h'0382 h'047f h'0400 h'0401 h'0402 h'04ff h'0480 h'0481 h'0481 h'07ff h'0780 h'0781 h'0782 h'087f h'0800 h'0801 h'0802 h'08ff h'0880 h'0881 h'0882 h'0bff h'0b80 h'0b81 h'0b82 h'0c7f h'0c00 h'0c01 h'0c02 h'0cff h'0c80 h'0c81 h'0c82 h'0fff h'0f80 h'0f81 h'0f82 h'107f h'1000 h'1001 h'1002 h'10ff h'1080 h'1081 h'1082 h'7fff h'7f80 h'7f81 h'7f82 programming unit: 128 bytes programming unit: 128 bytes programming unit: 128 bytes programming unit: 128 bytes programming unit: 128 bytes 1kbyte erase unit 1kbyte erase unit 1kbyte erase unit 1kbyte erase unit 28 kbytes erase unit figure 7.1 flash memory block configuration 7.2 register descriptions the flash memory has th e following registers. ? flash memory control register 1 (flmcr1) ? flash memory control register 2 (flmcr2) ? erase block register 1 (ebr1) ? flash memory power control register (flpwcr) ? flash memory enable register (fenr)
section 7 rom rev.5.00 nov. 02, 2005 page 89 of 418 rej09b0028-0500 7.2.1 flash memory control register 1 (flmcr1) flmcr1 is a register that makes the flash memory change to program mode, program-verify mode, erase mode, or erase-verify mode. for detail s on register setting, refer to section 7.4, flash memory programming/erasing. bit bit name initial value r/w description 7 ? 0 ? reserved this bit is always read as 0. 6 swe 0 r/w software write enable when this bit is set to 1, flash memory programming/erasing is enabled. when this bit is cleared to 0, other flmcr1 register bits and all ebr1 bits cannot be set. 5 esu 0 r/w erase setup when this bit is set to 1, the flash memory changes to the erase setup state. when it is cleared to 0, the erase setup state is cancelled. set this bit to 1 before setting the e bit to 1 in flmcr1. 4 psu 0 r/w program setup when this bit is set to 1, the flash memory changes to the program setup state. when it is cleared to 0, the program setup state is cancelled. set this bit to 1 before setting the p bit in flmcr1. 3 ev 0 r/w erase-verify when this bit is set to 1, the flash memory changes to erase-verify mode. when it is cleared to 0, erase-verify mode is cancelled. 2 pv 0 r/w program-verify when this bit is set to 1, the flash memory changes to program-verify mode. when it is cleared to 0, program- verify mode is cancelled. 1 e 0 r/w erase when this bit is set to 1, and while the swe=1 and esu=1 bits are 1, the flash memory changes to erase mode. when it is cleared to 0, erase mode is cancelled.
section 7 rom rev.5.00 nov. 02, 2005 page 90 of 418 rej09b0028-0500 bit bit name initial value r/w description 0 p 0 r/w program when this bit is set to 1, and while the swe=1 and psu=1 bits are 1, the flash memory changes to program mode. when it is cleared to 0, program mode is cancelled. 7.2.2 flash memory control register 2 (flmcr2) flmcr2 is a register that displa ys the state of flash memory programming/erasing. flmcr2 is a read-only register, and should not be written to. bit bit name initial value r/w description 7 fler 0 r flash memory error indicates that an error has occurred during an operation on flash memory (programming or erasing). when fler is set to 1, flash memory goes to the error-protection state. see 7.5.3, error protection, for details. 6 to 0 ? all 0 ? reserved these bits are always read as 0.
section 7 rom rev.5.00 nov. 02, 2005 page 91 of 418 rej09b0028-0500 7.2.3 erase block register 1 (ebr1) ebr1 specifies the flash memory er ase area block. ebr1 is initia lized to h'00 when the swe bit in flmcr1 is 0. do not set more than one bit at a time, as this will cause all the bits in ebr1 to be automatically cleared to 0. bit bit name initial value r/w description 7 to 5 ? all 0 ? reserved these bits are always read as 0. 4 eb4 0 r/w when this bit is set to 1, 28 kbytes of h'1000 to h'7fff will be erased. 3 eb3 0 r/w when this bit is set to 1, 1 kbyte of h'0c00 to h'0fff will be erased. 2 eb2 0 r/w when this bit is set to 1, 1 kbyte of h'0800 to h'0bff will be erased. 1 eb1 0 r/w when this bit is set to 1, 1 kbyte of h'0400 to h'07ff will be erased. 0 eb0 0 r/w when this bit is set to 1, 1 kbyte of h'0000 to h'03ff will be erased.
section 7 rom rev.5.00 nov. 02, 2005 page 92 of 418 rej09b0028-0500 7.2.4 flash memory power control register (flpwcr) flpwcr enables or disables a transition to th e flash memory power-down mode when the lsi switches to subactive mode. there are two modes: mode in which operation of the power supply circuit of flash memory is partly halted in power-down mode and flash memory can be read, and mode in which even if a transition is made to subactive mode, operation of the power supply circuit of flash memory is retain ed and flash memory can be read. bit bit name initial value r/w description 7 pdwnd 0 r/w power-down disable when this bit is 0 and a transition is made to subactive mode, the flash memory ent ers the power-down mode. when this bit is 1, the flash memory remains in the normal mode even after a transition is made to subactive mode. 6 to 0 ? all 0 ? reserved these bits are always read as 0. 7.2.5 flash memory enable register (fenr) bit 7 (flshe) in fenr enables or disables the cpu access to the flash memo ry control registers, flmcr1, flmcr2, ebr1, and flpwcr. bit bit name initial value r/w description 7 flshe 0 r/w flash memory control register enable flash memory control registers can be accessed when this bit is set to 1. flash memory control registers cannot be accessed when this bit is set to 0. 6 to 0 ? all 0 ? reserved these bits are always read as 0.
section 7 rom rev.5.00 nov. 02, 2005 page 93 of 418 rej09b0028-0500 7.3 on-board programming modes there are two modes for programming/erasing of the flash memory; boot mode, which enables on- board programming/erasing, and programmer mode, in which programming/erasing is performed with a prom programmer. on-board programming/erasing can also be performed in user program mode. at reset-start in reset mode, this lsi changes to a mode depending on the test pin settings, nmi pin settings, and input level of each port, as shown in table 7.1. the input level of each pin must be defined four states before the reset ends. when changing to boot mode, the boot program built into this lsi is initiated. the boot program transfers the programming control program from the externally-connected host to on-chip ram via sci3. after erasing the entir e flash memory, the programming control program is executed. this can be used for programming initial values in the on-board state or for a forcible return when programming/erasing can no longer be done in user program mode. in user program mode, individual blocks can be erased and programmed by branching to the user program/erase control program prepared by the user. table 7.1 setting programming modes test nmi p85 pb0 pb1 pb2 lsi state after reset end 0 1 x x x x user mode 0 0 1 x x x boot mode 1 x x 0 0 0 programmer mode legend: x : don?t care. 7.3.1 boot mode table 7.2 shows the boot mode operations between reset end and branching to the programming control program. 1. when boot mode is used, the flash memory programming control program must be prepared in the host beforehand. prepare a programming control program in accordance with the description in section 7.4, flash memory programming/erasing. 2. sci3 should be set to asynchronous mode, and the transfer format as follows: 8-bit data, 1 stop bit, and no parity. 3. when the boot program is initiated, the chip measures the low-level period of asynchronous sci communication data (h'00) transmitted continuously from the host. the chip then calculates the bit rate of transmi ssion from the host, and adjusts th e sci3 bit rate to match that of the host. the reset should end with the rxd pin high. the rxd and txd pins should be
section 7 rom rev.5.00 nov. 02, 2005 page 94 of 418 rej09b0028-0500 pulled up on the board if necessary. after the reset is complete, it takes approximately 100 states before the chip is ready to measure the low-level period. 4. after matching the bit rates, the chip transmits one h'00 byte to the host to indicate the completion of bit rate adjustment. the host should confirm that this adjustment end indication (h'00) has been received normally, and transmit on e h'55 byte to the chip. if reception could not be performed normally, initia te boot mode again by a reset. depending on the host's transfer bit rate and system clock frequency of this lsi, there will be a discrepancy between the bit rates of the host and the chip. to oper ate the sci properly, set the host's transfer bit rate and system clock frequency of this ls i within the ranges listed in table 7.3. 5. in boot mode, a part of the on-chip ram area is used by the boot program. the area h'f780 to h'feef is the area to which the programming control program is transferred from the host. the boot program area cannot be used until the execution state in boot mode switches to the programming control program. 6. before branching to the programming control pr ogram, the chip terminat es transfer operations by sci3 (by clearing the re and te bits in scr to 0), however the adjusted bit rate value remains set in brr. therefore, the programming control program can still use it for transfer of write data or verify data with the host. the txd pin is high (pcr22 = 1, p22 = 1). the contents of the cpu general registers are undefined immediately after branching to the programming control program. these registers must be initialized at the beginning of the programming control program, as the stack pointe r (sp), in particular, is used implicitly in subroutine calls, etc. 7. boot mode can be cleared by a reset. end the reset after driving the reset pin low, waiting at least 20 states, and then setting the nmi pin. boot mode is also cleared when a wdt overflow occurs. 8. do not change the test pin and nmi pin input levels in boot mode.
section 7 rom rev.5.00 nov. 02, 2005 page 95 of 418 rej09b0028-0500 table 7.2 boot mode operation communication contents processing contents host operation lsi operation processing contents continuously transmits data h'00 at specified bit rate. branches to boot program at reset-start. boot program initiation h'00, h'00 . . . h'00 h'00 h'55 transmits data h'55 when data h'00 is received error-free. h'xx transmits number of bytes (n) of programming control program to be transferred as 2-byte data (low-order byte following high-order byte) transmits 1-byte of programming control program (repeated for n times) h'aa reception h'aa reception upper bytes, lower bytes echoback echoback h'aa h'aa branches to programming control program transferred to on-chip ram and starts execution. transmits data h'aa to host. checks flash memory data, erases all flash memory blocks in case of written data existing, and transmits data h'aa to host. (if erase could not be done, transmits data h'ff to host and aborts operation.) h'ff boot program erase error item boot mode initiation measures low-level period of receive data h'00. calculates bit rate and sets brr in sci3. transmits data h'00 to host as adjustment end indication. h'55 reception. bit rate adjustment echobacks the 2-byte data received to host. echobacks received data to host and also transfers it to ram. (repeated for n times) transfer of number of bytes of programming control program flash memory erase
section 7 rom rev.5.00 nov. 02, 2005 page 96 of 418 rej09b0028-0500 table 7.3 system clock frequencies for which automatic adjustment of lsi bit rate is possible host bit rate system cloc k frequency range of lsi 19,200 bps 16 to 20 mhz 9,600 bps 8 to 16 mhz 4,800 bps 4 to 16 mhz 2,400 bps 2 to 16 mhz 7.3.2 programming/erasing in user program mode on-board programming/erasing of an individual flash memory block can also be performed in user program mode by branching to a user program/erase control program. the user must set branching conditions and provide on-board means of supplying programming data. the flash memory must contain the user program/erase control program or a program that provides the user program/erase control program from external memory. as the flash memory itself cannot be read during programming/erasing, transfer the user program/erase control program to on-chip ram, as in boot mode. figure 7.2 shows a sample procedure for programming/erasing in user program mode. prepare a user program/erase control program in accordance with the description in section 7.4, flash memory programming/erasing.
section 7 rom rev.5.00 nov. 02, 2005 page 97 of 418 rej09b0028-0500 ye s no program/erase? transfer user program/erase control program to ram reset-start branch to user program/erase control program in ram execute user program/erase control program (flash memory rewrite) branch to flash memory application program branch to flash memory application program figure 7.2 programming/erasing flowchart example in user program mode
section 7 rom rev.5.00 nov. 02, 2005 page 98 of 418 rej09b0028-0500 7.4 flash memory programming/erasing a software method using the cpu is employed to program and erase fl ash memory in the on- board programming modes. depending on the flmcr1 setting, the flash memory operates in one of the following four modes: program mode, program-verify mode, erase mode, and erase-verify mode. the programming control program in boot mode and the user program/erase control program in user program mode use these operating modes in combination to perform programming/erasing. flash memory programming and erasing should be performed in accordance with the descriptions in section 7.4. 1, program/program-veri fy and sect ion 7.4.2, erase/erase-verify, respectively. 7.4.1 program/program-verify when writing data or programs to the flash memory, the program/program-verify flowchart shown in figure 7.3 should be followed. performing programming operations according to this flowchart will enable data or programs to be written to the flash memory without subjecting the chip to voltage stress or sacrificing program data reliability. 1. programming must be done to an empty address. do not reprogram an address to which programming has already been performed. 2. programming should be carried out 128 bytes at a time. a 128-byte data transfer must be performed even if writing fewer than 128 bytes. in this case, h'ff data must be written to the extra addresses. 3. prepare the following data storage areas in ram: a 128-byte programming data area, a 128- byte reprogramming data area, and a 128-byte additional-programming data area. perform reprogramming data computation according to table 7.4, and additional programming data computation according to table 7.5. 4. consecutively transfer 128 bytes of data in byte units from the reprogramming data area or additional-programming data ar ea to the flash memory. the program address and 128-byte data are latched in the flash memory. the lower 8 bits of the start addr ess in the flash memory destination area must be h'00 or h'80. 5. the time during which the p bit is set to 1 is the programming time. table 7.6 shows the allowable programming times. 6. the watchdog timer (wdt) is set to prevent overprogramming due to program runaway, etc. an overflow cycle of approximately 6.6 ms is allowed. 7. for a dummy write to a verify address, write 1-byte data h'ff to an address whose lower 2 bits are b'00. verify data can be read in words or in longwords from the address to which a dummy write was performed.
section 7 rom rev.5.00 nov. 02, 2005 page 99 of 418 rej09b0028-0500 8. the maximum number of repetitions of the pr ogram/program-verify sequence of the same bit is 1,000. start end of programming notes: * the rts instruction must not be used during the following 1. and 2. periods. 1. a period between 128-byte data programming to flash memory and the p bit clearing 2. a period between dummy writing of h'ff to a verify address and verify data reading set swe bit in flmcr1 write pulse application subroutine wait 1 s apply write pulse * end sub set psu bit in flmcr1 wdt enable disable wdt wait 50 s set p bit in flmcr1 wait (wait time=programming time) clear p bit in flmcr1 wait 5 s clear psu bit in flmcr1 wait 5 s n= 1 m= 0 no no no yes yes yes yes wait 4 s wait 2 s wait 2 s apply write pulse set pv bit in flmcr1 set block start address as verify address h'ff dummy write to verify address read verify data verify data = write data? reprogram data computation additional-programming data computation clear pv bit in flmcr1 clear swe bit in flmcr1 m = 1 m= 0 ? increment address programming failure no clear swe bit in flmcr1 wait 100 s no yes n 6? no yes n 6 ? wait 100 s n 1000 ? n n + 1 write 128-byte data in ram reprogram data area consecutively to flash memory store 128-byte program data in program data area and reprogram data area apply write pulse sub-routine-call 128-byte data verification completed? successively write 128-byte data from additional- programming data area in ram to flash memory * figure 7.3 program/program-verify flowchart
section 7 rom rev.5.00 nov. 02, 2005 page 100 of 418 rej09b0028-0500 table 7.4 reprogram data computation table program data verify data reprogram data comments 0 0 1 programming completed 0 1 0 reprogram bit 1 0 1 ? 1 1 1 remains in erased state table 7.5 additional-program data computation table reprogram data verify data additional-program data comments 0 0 0 additional-program bit 0 1 1 no additional programming 1 0 1 no additional programming 1 1 1 no additional programming table 7.6 programming time n (number of writes) programming time in additional programming comments 1 to 6 30 10 7 to 1,000 200 ? note: time shown in s. 7.4.2 erase/erase-verify when erasing flash memory, the erase/erase-veri fy flowchart shown in figure 7.4 should be followed. 1. prewriting (setting erase block da ta to all 0s) is not necessary. 2. erasing is performed in block units. make only a single-bit specification in the erase block register (ebr1). to erase multiple blocks, each block must be erased in turn. 3. the time during which the e bit is set to 1 is the flash memory erase time. 4. the watchdog timer (wdt) is set to prevent overerasing due to program runaway, etc. an overflow cycle of approximately 19.8 ms is allowed.
section 7 rom rev.5.00 nov. 02, 2005 page 101 of 418 rej09b0028-0500 5. for a dummy write to a verify address, write 1-byte data h'ff to an address whose lower two bits are b'00. verify data can be read in lo ngwords from the address to which a dummy write was performed. 6. if the read data is not erased successfully, se t erase mode again, and repeat the erase/erase- verify sequence as before. the maximum numb er of repetitions of the erase/erase-verify sequence is 100. 7.4.3 interrupt handli ng when programming/erasing flash memory all interrupts, including the nmi interrupt, are disabled while flash memory is being programmed or erased, or while the boot program is executing, for the following three reasons: 1. interrupt during programming/erasing may cause a violation of the programming or erasing algorithm, with the result that normal operation cannot be assured. 2. if interrupt exception handling starts before the vector address is written or during programming/erasing, a correct vector cannot be fetched and the cpu malfunctions. 3. if an interrupt occurs during boot program execution, normal boot mode sequence cannot be carried out.
section 7 rom rev.5.00 nov. 02, 2005 page 102 of 418 rej09b0028-0500 erase start set ebr1 enable wdt wait 1 s wait 100 s swe bit 1 n 1 esu bit 1 e bit 1 wait 10 ms e bit 0 wait 10 s esu bit 10 10 s disable wdt read verify data increment address verify data + all 1s ? last address of block ? all erase block erased ? set block start address as verify address h'ff dummy write to verify address wait 20 s wait 2 s ev bit 1 wait 100 s end of erasing note: * the rts instruction must not be used during a period between dummy writing of h'ff to a verify address and verify data reading. swe bit 0 wait 4 s ev bit 0 n 100 ? wait 100 s erase failure swe bit 0 wait 4 s ev bit 0 n n + 1 ye s no ye s ye s ye s ye s no no no * figure 7.4 erase/erase-verify flowchart
section 7 rom rev.5.00 nov. 02, 2005 page 103 of 418 rej09b0028-0500 7.5 program/erase protection there are three kinds of flash memory program/erase protection; hardware protection, software protection, and error protection. 7.5.1 hardware protection hardware protection refers to a state in which programming/erasing of flash memory is forcibly disabled or aborted because of a transition to reset, subactive mode, subsleep mode, or standby mode. flash memory control register 1 (flmcr1), flash memory control register 2 (flmcr2), and erase block register 1 (ebr1) ar e initialized. in a reset via the res pin, the reset state is not entered unless the res pin is held low until oscillation stab ilizes after powering on. in the case of a reset during operation, hold the res pin low for the res pulse width specified in the ac characteristic s section. 7.5.2 software protection software protection can be implemented against programming/erasing of all flash memory blocks by clearing the swe bit in flmcr1. when software protection is in effect, setting the p or e bit in flmcr1 does not cause a transition to prog ram mode or erase mode. by setting the erase block register 1 (ebr1), erase protection can be set for individual blocks. when ebr1 is set to h'00, erase protection is set for all blocks. 7.5.3 error protection in error protection, an error is detected when cpu runaway occurs during flash memory programming/erasing, or operation is not performed in accordance with the program/erase algorithm, and the prog ram/erase operation is aborted. aborting the program/erase operation prevents damage to the flash memory due to overprogramming or overerasing. when the following errors are de tected during programming/eras ing of flash memory, the fler bit in flmcr2 is set to 1, and the error protection state is entered. ? when the flash memory of the relevant address area is read during programming/erasing (including vector read and instruction fetch) ? immediately after exception handling excluding a reset during programming/erasing ? when a sleep instruction is executed during programming/erasing the flmcr1, flmcr2, and ebr1 settings are retained, however program mode or erase mode is aborted at the point at which the error occurr ed. program mode or erase mode cannot be re-
section 7 rom rev.5.00 nov. 02, 2005 page 104 of 418 rej09b0028-0500 entered by re-setting the p or e bit. however, pv and ev bit setting is enabled, and a transition can be made to verify mode. error protection can be cleared only by a reset. 7.6 programmer mode in programmer mode, a prom programmer can be used to perform programming/erasing via a socket adapter, just as a discrete flash memo ry. use a prom programmer that supports the mcu device type with the on-chip 64-kbyte flash memory (fztat64v5). 7.7 power-down states for flash memory in user mode, the flash memory will operate in either of the following states: ? ? ?
section 7 rom rev.5.00 nov. 02, 2005 page 105 of 418 rej09b0028-0500 table 7.7 flash memory operating states flash memory operating state lsi operating state pdwnd = 0 (initial value) pdwnd = 1 active mode normal operating mode normal operating mode subactive mode power-down mode normal operating mode sleep mode normal operating mode normal operating mode subsleep mode standby mode standby mode standby mode standby mode standby mode
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section 8 ram ram0300a_000120030300 rev.5.00 nov. 02, 2005 page 107 of 418 rej09b0028-0500 section 8 ram this lsi has an on-chip high-speed static ram. the ram is connected to the cpu by a 16-bit data bus, enabling two-state access by the cpu to both byte data and word data. product classification ram size ram address flash memory version (f-ztat tm version) h8/3694f 2 kbytes h'f780 to h'ff7f * mask-rom version h8/3694 1 kbyte h'fb80 to h'ff7f h8/3693 1 kbyte h'fb80 to h'ff7f h8/3692 512 kbytes h'fd80 to h'ff7f h8/3691 512 kbytes h'fd80 to h'ff7f h8/3690 512 kbytes h'fd80 to h'ff7f flash memory version 2 kbytes h'f780 to h'ff7f * eeprom stacked version mask-rom version h8/3694n 1 kbyte h'fb80 to h'ff7f note: * when the e7 or e8 is used, area h 'f780 to h'fb7f must not be accessed.
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section 9 i/o ports rev.5.00 nov. 02, 2005 page 109 of 418 rej09b0028-0500 section 9 i/o ports the group of this lsi has twenty-nine general i/o ports (twenty-seven general i/o ports in the h8/3694n) and eight general input-only ports. port 8 is a large current port, which can drive 20 ma (@v ol = 1.5 v) when a low level signal is output. any of these ports can become an input port immediately after a reset. they can also be used as i/o pins of the on-chip peripheral modules or external interrupt input pins, and these functions can be switched depending on the register settings. the registers for selecting these functions can be divided into two types: those included in i/o ports and those included in each on-ch ip peripheral module. general i/o ports are comprised of the port control register for controlling inputs/outputs and the port data register for storing output data and can select inputs/outputs in bit units. for functions in each port, see appendix b.1, i/o port block diagrams. for the execution of bit manipulation instructions to the port control register and port data register, see section 2.8.3, bit manipulation instruction. 9.1 port 1 port 1 is a general i/o port also functioning as irq interrupt input pins, a timer a output pin, and a timer v input pin. figure 9.1 shows its pin configuration. p17/ irq3 /trgv p16/ irq2 p15/ irq1 p14/ irq0 p12 p11 p10/tmow port 1 figure 9.1 port 1 pin configuration port 1 has the following registers. ? ? ? ?
section 9 i/o ports rev.5.00 nov. 02, 2005 page 110 of 418 rej09b0028-0500 9.1.1 port mode register 1 (pmr1) pmr1 switches the functions of pins in port 1 and port 2. bit bit name initial value r/w description 7 irq3 0 r/w p17/ irq3 /trgv pin function switch this bit selects whether pin p17/ irq3 /trgv is used as p17 or as irq3 /trgv. 0: general i/o port 1: irq3 /trgv input pin 6 irq2 0 r/w p16/ irq2 pin function switch this bit selects whether pin p16/ irq2 is used as p16 or as irq2 . 0: general i/o port 1: irq2 input pin 5 irq1 0 r/w p15/ irq1 pin function switch this bit selects whether pin p15/ irq1 is used as p15 or as irq1 . 0: general i/o port 1: irq1 input pin 4 irq0 0 r/w p14/ irq0 pin function switch this bit selects whether pin p14/ irq0 is used as p14 or as irq0 . 0: general i/o port 1: irq0 input pin 3, 2 ? all 1 ? reserved these bits are always read as 1. 1 txd 0 r/w p22/txd pin function switch this bit selects whether pin p22/txd is used as p22 or as txd. 0: general i/o port 1: txd output pin 0 tmow 0 r/w p10/tmow pin function switch this bit selects whether pin p10/tmow is used as p10 or as tmow. 0: general i/o port 1: tmow output pin
section 9 i/o ports rev.5.00 nov. 02, 2005 page 111 of 418 rej09b0028-0500 9.1.2 port control register 1 (pcr1) pcr1 selects inputs/outputs in bit units for pins to be used as general i/o ports of port 1. bit bit name initial value r/w description 7 6 5 4 3 2 1 0 pcr17 pcr16 pcr15 pcr14 ? pcr12 pcr11 pcr10 0 0 0 0 ? 0 0 0 w w w w ? w w w when the corresponding pin is designated in pmr1 as a general i/o pin, setting a pcr1 bit to 1 makes the corresponding pin an output port, while clearing the bit to 0 makes the pin an input port. bit 3 is a reserved bit. 9.1.3 port data register 1 (pdr1) pdr1 is a general i/o port data register of port 1. bit bit name initial value r/w description 7 6 5 4 3 2 1 0 p17 p16 p15 p14 ? p12 p11 p10 0 0 0 0 1 0 0 0 r/w r/w r/w r/w ? r/w r/w r/w pdr1 stores output data for port 1 pins. if pdr1 is read while pcr1 bi ts are set to 1, the value stored in pdr1 are read. if pdr1 is read while pcr1 bits are cleared to 0, the pin stat es are read regardless of the value stored in pdr1. bit 3 is a reserved bit. this bit is always read as 1.
section 9 i/o ports rev.5.00 nov. 02, 2005 page 112 of 418 rej09b0028-0500 9.1.4 port pull-up control register 1 (pucr1) pucr1 controls the pull-up mos in bit units of the pins set as the input ports. bit bit name initial value r/w description 7 6 5 4 3 2 1 0 pucr17 pucr16 pucr15 pucr14 ? pucr12 pucr11 pucr10 0 0 0 0 1 0 0 0 r/w r/w r/w r/w ? r/w r/w r/w only bits for which pcr1 is cleared are valid. the pull-up mos of p17 to p14 and p12 to p10 pins enter the on- state when these bits are set to 1, while they enter the off-state when these bits are cleared to 0. bit 3 is a reserved bit. this bit is always read as 1. 9.1.5 pin functions the correspondence between the register specification and the port functions is shown below. p17/ irq3 /trgv pin register pmr1 pcr1 bit name irq3 pcr17 pin function setting value 0 0 p17 input pin 1 p17 output pin 1 x irq3 input/trgv input pin legend: x: don't care. p16/ irq2 pin register pmr1 pcr1 bit name irq2 pcr16 pin function setting value 0 0 p16 input pin 1 p16 output pin 1 x irq2 input pin legend: x: don't care.
section 9 i/o ports rev.5.00 nov. 02, 2005 page 113 of 418 rej09b0028-0500 p15/ irq1 pin register pmr1 pcr1 bit name irq1 pcr15 pin function setting value 0 0 p15 input pin 1 p15 output pin 1 x irq1 input pin legend: x: don't care. p14/ irq0 pin register pmr1 pcr1 bit name irq0 pcr14 pin function setting value 0 0 p14 input pin 1 p14 output pin 1 x irq0 input pin legend: x: don't care. p12 pin register pcr1 bit name pcr12 pin function 0 p12 input pin setting value 1 p12 output pin p11 pin register pcr1 bit name pcr11 pin function 0 p11 input pin setting value 1 p11 output pin
section 9 i/o ports rev.5.00 nov. 02, 2005 page 114 of 418 rej09b0028-0500 p10/tmow pin register pmr1 pcr1 bit name tmow pcr10 pin function setting value 0 0 p10 input pin 1 p10 output pin 1 x tmow output pin legend: x: don't care. 9.2 port 2 port 2 is a general i/o port also functioning as a sci3 i/o pin. each pin of the port 2 is shown in figure 9.2. the register settings of pmr1 and sci3 have priority for functions of the pins for both uses. p22/txd p21/rxd p20/sck3 port 2 figure 9.2 port 2 pin configuration port 2 has the following registers. ? port control register 2 (pcr2) ? port data register 2 (pdr2)
section 9 i/o ports rev.5.00 nov. 02, 2005 page 115 of 418 rej09b0028-0500 9.2.1 port control register 2 (pcr2) pcr2 selects inputs/outputs in bit units for pins to be used as general i/o ports of port 2. bit bit name initial value r/w description 7 to 3 ? ? ? reserved 2 1 0 pcr22 pcr21 pcr20 0 0 0 w w w when each of the port 2 pins p22 to p20 functions as an general i/o port, setting a pcr2 bit to 1 makes the corresponding pin an output port, while clearing the bit to 0 makes the pin an input port. 9.2.2 port data register 2 (pdr2) pdr2 is a general i/o port data register of port 2. bit bit name initial value r/w description 7 to 3 ? all 1 ? reserved these bits are always read as 1. 2 1 0 p22 p21 p20 0 0 0 r/w r/w r/w pdr2 stores output data for port 2 pins. if pdr2 is read while pcr2 bi ts are set to 1, the value stored in pdr2 is read. if pdr2 is read while pcr2 bits are cleared to 0, the pin stat es are read regardless of the value stored in pdr2.
section 9 i/o ports rev.5.00 nov. 02, 2005 page 116 of 418 rej09b0028-0500 9.2.3 pin functions the correspondence between the register specification and the port functions is shown below. p22/txd pin register pmr1 pcr2 bit name txd pcr22 pin function setting value 0 0 p22 input pin 1 p22 output pin 1 x txd output pin legend: x: don't care. p21/rxd pin register scr3 pcr2 bit name re pcr21 pin function setting value 0 0 p21 input pin 1 p21 output pin 1 x rxd input pin legend: x: don't care. p20/sck3 pin register scr3 smr pcr2 bit name cke1 cke0 com pcr20 pin function setting value 0 0 0 0 p20 input pin 1 p20 output pin 0 0 1 x sck3 output pin 0 1 x x sck3 output pin 1 x x x sck3 input pin legend: x: don't care.
section 9 i/o ports rev.5.00 nov. 02, 2005 page 117 of 418 rej09b0028-0500 9.3 port 5 port 5 is a general i/o port also functioning as an i 2 c bus interface i/o pin, an a/d trigger input pin, wakeup interrupt input pin. each pin of the port 5 is shown in figure 9.3. the register setting of the i 2 c bus interface register has priority for functions of the pins p57/scl and p56/sda. since the output buffer for pins p56 and p57 has the nmos push-pull structure, it differs from an output buffer with the cmos structure in the high-level output characteristics (see section 21, electrical characteristics). p57/scl p56/sda p55/ wkp5 / adtrg p54/ wkp4 p53/ wkp3 p52/ wkp2 p51/ wkp1 p50/ wkp0 h8/3694 h8/3694n port 5 scl sda p55/ wkp5 / adtr g p54/ wkp4 p53/ wkp3 p52/ wkp2 p51/ wkp1 p50/ wkp0 port 5 figure 9.3 port 5 pin configuration port 5 has the following registers. ? port mode register 5 (pmr5) ? port control register 5 (pcr5) ? port data register 5 (pdr5) ? port pull-up control register 5 (pucr5)
section 9 i/o ports rev.5.00 nov. 02, 2005 page 118 of 418 rej09b0028-0500 9.3.1 port mode register 5 (pmr5) pmr5 switches the functions of pins in port 5. bit bit name initial value r/w description 7, 6 ? all 0 ? reserved these bits are always read as 0. 5 wkp5 0 r/w p55/ wkp5 / adtrg pin function switch selects whether pin p55/ wkp5 / adtrg is used as p55 or as wkp5 / adtrg input. 0: general i/o port 1: wkp5 / adtrg input pin 4 wkp4 0 r/w p54/ wkp4 pin function switch selects whether pin p54/ wkp4 is used as p54 or as wkp4 . 0: general i/o port 1: wkp4 input pin 3 wkp3 0 r/w p53/ wkp3 pin function switch selects whether pin p53/ wkp3 is used as p53 or as wkp3 . 0: general i/o port 1: wkp3 input pin 2 wkp2 0 r/w p52/ wkp2 pin function switch selects whether pin p52/ wkp2 is used as p52 or as wkp2 . 0: general i/o port 1: wkp2 input pin 1 wkp1 0 r/w p51/ wkp1 pin function switch selects whether pin p51/ wkp1 is used as p51 or as wkp1 . 0: general i/o port 1: wkp1 input pin 0 wkp0 0 r/w p50/ wkp0 pin function switch selects whether pin p50/ wkp0 is used as p50 or as wkp0 . 0: general i/o port 1: wkp0 input pin
section 9 i/o ports rev.5.00 nov. 02, 2005 page 119 of 418 rej09b0028-0500 9.3.2 port control register 5 (pcr5) pcr5 selects inputs/outputs in bit units for pins to be used as general i/o ports of port 5. bit bit name initial value r/w description 7 6 5 4 3 2 1 0 pcr57 pcr56 pcr55 pcr54 pcr53 pcr52 pcr51 pcr50 0 0 0 0 0 0 0 0 w w w w w w w w when each of the port 5 pins p57 to p50 functions as an general i/o port, setting a pcr5 bit to 1 makes the corresponding pin an output port, while clearing the bit to 0 makes the pin an input port. note: the pcr57 and pcr56 bits should not be set to 1 in the h8/3694n. 9.3.3 port data register 5 (pdr5) pdr5 is a general i/o port data register of port 5. bit bit name initial value r/w description 7 6 5 4 3 2 1 0 p57 p56 p55 p54 p53 p52 p51 p50 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w stores output data for port 5 pins. if pdr5 is read while pcr5 bi ts are set to 1, the value stored in pdr5 are read. if pdr5 is read while pcr5 bits are cleared to 0, the pin stat es are read regardless of the value stored in pdr5. note: the p57 and p56 bits should not be set to 1 in the h8/3694n.
section 9 i/o ports rev.5.00 nov. 02, 2005 page 120 of 418 rej09b0028-0500 9.3.4 port pull-up control register 5 (pucr5) pucr5 controls the pull-up mos in bit units of the pins set as the input ports. bit bit name initial value r/w description 7, 6 ? all 0 ? reserved these bits are always read as 0. 5 4 3 2 1 0 pucr55 pucr54 pucr53 pucr52 pucr51 pucr50 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w only bits for which pcr5 is cleared are valid. the pull-up mos of the corresponding pi ns enter the on-state when these bits are set to 1, while they enter the off-state when these bits are cleared to 0. 9.3.5 pin functions the correspondence between the register specification and the port functions is shown below. p57/scl pin register iccr1 pcr5 bit name ice pcr57 pin function setting value 0 0 p57 input pin 1 p57 output pin 1 x scl i/o pin legend: x: don't care. scl performs the nmos open-drain output, that enables a direct bus drive.
section 9 i/o ports rev.5.00 nov. 02, 2005 page 121 of 418 rej09b0028-0500 p56/sda pin register iccr1 pcr5 bit name ice pcr56 pin function setting value 0 0 p56 input pin 1 p56 output pin 1 x sda i/o pin legend: x: don't care. sda performs the nmos open-drain output, that enables a direct bus drive. p55/ wkp5 / adtrg pin register pmr5 pcr5 bit name wkp5 pcr55 pin function setting value 0 0 p55 input pin 1 p55 output pin 1 x wkp5 / adtrg input pin legend: x: don't care. p54/ wkp4 pin register pmr5 pcr5 bit name wkp4 pcr54 pin function setting value 0 0 p54 input pin 1 p54 output pin 1 x wkp4 input pin legend: x: don't care.
section 9 i/o ports rev.5.00 nov. 02, 2005 page 122 of 418 rej09b0028-0500 p53/wkp3 pin register pmr5 pcr5 bit name wkp3 pcr53 pin function setting value 0 0 p53 input pin 1 p53 output pin 1 x wkp3 input pin legend: x: don't care. p52/wkp2 pin register pmr5 pcr5 bit name wkp2 pcr52 pin function setting value 0 0 p52 input pin 1 p52 output pin 1 x wkp2 input pin legend: x: don't care. p51/wkp1 pin register pmr5 pcr5 bit name wkp1 pcr51 pin function setting value 0 0 p51 input pin 1 p51 output pin 1 x wkp1 input pin legend: x: don't care.
section 9 i/o ports rev.5.00 nov. 02, 2005 page 123 of 418 rej09b0028-0500 p50/wkp0 pin register pmr5 pcr5 bit name wkp0 pcr50 pin function setting value 0 0 p50 input pin 1 p50 output pin 1 x wkp0 input pin legend: x: don't care. 9.4 port 7 port 7 is a general i/o port also functioning as a timer v i/o pin. each pin of the port 7 is shown in figure 9.4. the register setting of tcsrv in timer v has priority for functions of pin p76/tmov. the pins, p75/tmciv and p74/tmriv, are also functioning as timer v input ports that are connected to the timer v regardle ss of the register setting of port 7. p76/tmov p75/tmciv p74/tmriv port 7 figure 9.4 port 7 pin configuration port 7 has the following registers. ? port control register 7 (pcr7) ? port data register 7 (pdr7)
section 9 i/o ports rev.5.00 nov. 02, 2005 page 124 of 418 rej09b0028-0500 9.4.1 port control register 7 (pcr7) pcr7 selects inputs/outputs in bit units for pins to be used as general i/o ports of port 7. bit bit name initial value r/w description 7 ? ? ? reserved 6 5 4 pcr76 pcr75 pcr74 0 0 0 w w w setting a pcr7 bit to 1 makes the corresponding pin an output port, while clearing the bit to 0 makes the pin an input port. note that the tcsrv setting of the timer v has priority for deciding input/output direction of the p76/tmov pin. 3 to 0 ? ? ? reserved 9.4.2 port data register 7 (pdr7) pdr7 is a general i/o port data register of port 7. bit bit name initial value r/w description 7 ? 1 ? reserved this bit is always read as 1. 6 5 4 p76 p75 p74 0 0 0 r/w r/w r/w pdr7 stores output data for port 7 pins. if pdr7 is read while pcr7 bi ts are set to 1, the value stored in pdr7 is read. if pdr7 is read while pcr7 bits are cleared to 0, the pin stat es are read regardless of the value stored in pdr7. 3 to 0 ? all 1 ? reserved these bits are always read as 1.
section 9 i/o ports rev.5.00 nov. 02, 2005 page 125 of 418 rej09b0028-0500 9.4.3 pin functions the correspondence between the register specification and the port functions is shown below. p76/tmov pin register tcsrv pcr7 bit name os3 to os0 pcr76 pin function setting value 0000 0 p76 input pin 1 p76 output pin other than the above values x tmov output pin legend: x: don't care. p75/tmciv pin register pcr7 bit name pcr75 pin function setting value 0 p75 input/tmciv input pin 1 p75 output/tmciv input pin p74/tmriv pin register pcr7 bit name pcr74 pin function setting value 0 p74 input/tmriv input pin 1 p74 output/tmriv input pin
section 9 i/o ports rev.5.00 nov. 02, 2005 page 126 of 418 rej09b0028-0500 9.5 port 8 port 8 is a general i/o port also functioning as a timer w i/o pin. each pin of the port 8 is shown in figure 9.5. the register setting of the timer w has priority for functions of the pins p84/ftiod, p83/ftioc, p82/ftiob, and p81/ftioa. p80/ftci also functions as a timer w input port that is connected to the timer w regardless of the register setting of port 8. p87 p86 p85 p84/ftiod p83/ftioc p82/ftiob p81/ftioa p80/ftci port 8 figure 9.5 port 8 pin configuration port 8 has the following registers. ? port control register 8 (pcr8) ? port data register 8 (pdr8) 9.5.1 port control register 8 (pcr8) pcr8 selects inputs/outputs in bit units for pins to be used as general i/o ports of port 8. bit bit name initial value r/w description 7 6 5 4 3 2 1 0 pcr87 pcr86 pcr85 pcr84 pcr83 pcr82 pcr81 pcr80 0 0 0 0 0 0 0 0 w w w w w w w w when each of the port 8 pins p87 to p80 functions as an general i/o port, setting a pcr8 bit to 1 makes the corresponding pin an output port, while clearing the bit to 0 makes the pin an input port.
section 9 i/o ports rev.5.00 nov. 02, 2005 page 127 of 418 rej09b0028-0500 9.5.2 port data register 8 (pdr8) pdr8 is a general i/o port data register of port 8. bit bit name initial value r/w description 7 6 5 4 3 2 1 0 p87 p86 p85 p84 p83 p82 p81 p80 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w pdr8 stores output data for port 8 pins. if pdr8 is read while pcr8 bi ts are set to 1, the value stored in pdr8 is read. if pdr8 is read while pcr8 bits are cleared to 0, the pin stat es are read regardless of the value stored in pdr8. 9.5.3 pin functions the correspondence between the register specification and the port functions is shown below. p87 pin register pcr8 bit name pcr87 pin function setting value 0 p87 input pin 1 p87 output pin p86 pin register pcr8 bit name pcr86 pin function setting value 0 p86 input pin 1 p86 output pin
section 9 i/o ports rev.5.00 nov. 02, 2005 page 128 of 418 rej09b0028-0500 p85 pin register pcr8 bit name pcr85 pin function setting value 0 p85 input pin 1 p85 output pin p84/ftiod pin register tior1 pcr8 bit name iod2 iod1 iod0 pcr84 pin function setting value 0 0 0 0 p84 input/ftiod input pin 1 p84 output/ftiod input pin 0 0 1 x ftiod output pin 0 1 x x ftiod output pin 1 x x 0 p84 input/ftiod input pin 1 p84 output/ftiod input pin legend: x: don't care. p83/ftioc pin register tior1 pcr8 bit name ioc2 ioc1 ioc0 pcr83 pin function setting value 0 0 0 0 p83 input/ftioc input pin 1 p83 output/ftioc input pin 0 0 1 x ftioc output pin 0 1 x x ftioc output pin 1 x x 0 p83 input/ftioc input pin 1 p83 output/ftioc input pin legend: x: don't care.
section 9 i/o ports rev.5.00 nov. 02, 2005 page 129 of 418 rej09b0028-0500 p82/ftiob pin register tior0 pcr8 bit name iob2 iob1 iob0 pcr82 pin function setting value 0 0 0 0 p82 input/ftiob input pin 1 p82 output/ftiob input pin 0 0 1 x ftiob output pin 0 1 x x ftiob output pin 1 x x 0 p82 input/ftiob input pin 1 p82 output/ftiob input pin legend: x: don't care. p81/ftioa pin register tior0 pcr8 bit name ioa2 ioa1 ioa0 pcr81 pin function setting value 0 0 0 0 p81 input/ftioa input pin 1 p81 output/ftioa input pin 0 0 1 x ftioa output pin 0 1 x x ftioa output pin 1 x x 0 p81 input/ftioa input pin 1 p81 output/ftioa input pin legend: x: don't care. p80/ftci pin register pcr8 bit name pcr80 pin function setting value 0 p80 input/ftci input pin 1 p80 output/ftci input pin
section 9 i/o ports rev.5.00 nov. 02, 2005 page 130 of 418 rej09b0028-0500 9.6 port b port b is an input port also functioning as an a/d converter analog input pin. each pin of the port b is shown in figure 9.6. pb7/an7 pb6/an6 pb5/an5 pb4/an4 pb3/an3 pb2/an2 pb1/an1 pb0/an0 port b figure 9.6 port b pin configuration port b has the following register. ? port data register b (pdrb) 9.6.1 port data register b (pdrb) pdrb is a general input-only port data register of port b. bit bit name initial value r/w description 7 6 5 4 3 2 1 0 pb7 pb6 pb5 pb4 pb3 pb2 pb1 pb0 ? ? ? ? ? ? ? ? r r r r r r r r the input value of each pin is read by reading this register. however, if a port b pin is designated as an analog input channel by adcsr in a/d converter, 0 is read.
section 10 timer a tim08a0a_000020020200 rev.5.00 nov. 02, 2005 page 131 of 418 rej09b0028-0500 section 10 timer a timer a is an 8-bit timer with interval timing an d real-time clock time-base functions. the clock time-base function is available when a 32.768kh z crystal oscillator is connected. figure 10.1 shows a block diagram of timer a. 10.1 features ? ? ? interval timer ? clock time base ?
section 10 timer a rev.5.00 nov. 02, 2005 page 132 of 418 rej09b0028-0500 w tmow w /32 w /16 w /8 w /4 w /32 w /16 w /8 w /4 /8192, /4096, /2048, /512, /256, /128, /32, /8 w /128 w /4 1/4 psw pss tma tca irrta 8 * 64 * 128 * 256 * [legend] tma: timer mode register a tca: timer counter a irrta: timer a overflow interrupt request flag psw: prescaler w pss: prescaler s note: * can be selected only when the prescaler w output ( w /128) is used as the tca input clock. internal data bus figure 10.1 block diagram of timer a 10.2 input/output pins table 10.1 shows the timer a input/output pin. table 10.1 pin configuration name abbreviation i/o function clock output tmow output output of waveform generated by timer a output circuit
section 10 timer a rev.5.00 nov. 02, 2005 page 133 of 418 rej09b0028-0500 10.3 register descriptions timer a has the following registers. ? timer mode register a (tma) ? timer counter a (tca) 10.3.1 timer mode register a (tma) tma selects the operating mode, the divided clock output, and the input clock. bit bit name initial value r/w description 7 6 5 tma7 tma6 tma5 0 0 0 r/w r/w r/w clock output select 7 to 5 these bits select the clo ck output at the tmow pin. 000: /32 001: /16 010: /8 011: /4 100: w /32 101: w /16 110: w /8 111: w /4 for details on clock outputs, see section 10.4.3, clock output. 4 ? 1 ? reserved this bit is always read as 1. 3 tma3 0 r/w internal clock select 3 this bit selects the operating mode of the timer a. 0: functions as an interval timer to count the outputs of prescaler s. 1: functions as a clock-time base to count the outputs of prescaler w.
section 10 timer a rev.5.00 nov. 02, 2005 page 134 of 418 rej09b0028-0500 bit bit name initial value r/w description 2 1 0 tma2 tma1 tma0 0 0 0 r/w r/w r/w internal clock select 2 to 0 these bits select the clock input to tca when tma3 = 0. 000: /8192 001: /4096 010: /2048 011: /512 100: /256 101: /128 110: /32 111: /8 these bits select the overflow period when tma3 = 1 (when a 32.768 khz crystal oscillator with is used as w). 000: 1s 001: 0.5 s 010: 0.25 s 011: 0.03125 s 1xx: both psw and tca are reset legend: x: don't care. 10.3.2 timer counter a (tca) tca is an 8-bit readable up-counter, which is incremented by internal clock input. the clock source for input to this counter is selected by bits tma3 to tma0 in tma. tca values can be read by the cpu in active mode, but cannot be r ead in subactive mode. wh en tca overflows, the irrta bit in interrupt request register 1 (irr1) is set to 1. tca is cleared by setting bits tma3 and tma2 in tma to b?11. tca is initialized to h'00.
section 10 timer a rev.5.00 nov. 02, 2005 page 135 of 418 rej09b0028-0500 10.4 operation 10.4.1 interval timer operation when bit tma3 in tma is cleared to 0, timer a functions as an 8-bit interval timer. upon reset, tca is cleared to h'00 and bit tma3 is cleared to 0, so up-counting of timer a resume immediately as an interval timer. the clock input to timer a is selected by bits tma2 to tma0 in tma; any of eight in ternal clock signals output by prescaler s can be selected. after the count value in tca reaches h'ff, th e next clock signal input causes timer a to overflow, setting bit irrta to 1 in interrupt flag register 1 (irr1). if ienta = 1 in interrupt enable register 1 (ienr1), a cpu interrupt is re quested. at overflow, tca returns to h'00 and starts counting up again. in this mode timer a fu nctions as an interval timer that generates an overflow output at intervals of 256 input clock pulses. 10.4.2 clock time base operation when bit tma3 in tma is set to 1, timer a functions as a clock-timer base by counting clock signals output by prescaler w. when a clock si gnal is input after the tca counter value has become h'ff, timer a overflows and irrta in irr1 is set to 1. at that time, an interrupt request is generated to the cpu if ienta in the interrupt enable register 1 (ienr1) is 1. the overflow period of timer a is set by bits tma1 and tma0 in tma. a choice of four periods is available. in clock time base operation (tma3 = 1), setting bit tma2 to 1 clears both tca and prescaler w to h'00. 10.4.3 clock output setting bit tmow in port mode register 1 (pmr1) to 1 causes a clock signal to be output at pin tmow. eight different clock output signals can be selected by means of bits tma7 to tma5 in tma. the system clock divided by 32, 16, 8, or 4 can be output in active mode and sleep mode. a 32.768 khz signal divided by 32, 16, 8, or 4 can be output in active mode, sleep mode, and subactive mode. 10.5 usage note when the clock time base function is selected as th e internal clock of tca in active mode or sleep mode, the internal clock is not synchronous with the system clock, so it is synchronized by a synchronizing circuit. this may result in a maximum error of 1/ (s) in the count cycle.
section 10 timer a rev.5.00 nov. 02, 2005 page 136 of 418 rej09b0028-0500
section 11 timer v tim08v0a_000120030300 rev.5.00 nov. 02, 2005 page 137 of 418 rej09b0028-0500 section 11 timer v timer v is an 8-bit timer based on an 8-bit counter. timer v counts external events. compare- match signals with two registers can also be used to reset the counter, request an interrupt, or output a pulse signal with an arbitrary duty cycle. counting can be initiated by a trigger input at the trgv pin, enabling pulse output control to be synchronized to the trigger, with an arbitrary delay from the trigger input. figure 11.1 shows a block diagram of timer v. 11.1 features ? ? ? ? ?
section 11 timer v rev.5.00 nov. 02, 2005 page 138 of 418 rej09b0028-0500 trgv tmciv tmriv tmov trigger control clock select clear control output control pss tcrv1 tcorb comparator tcntv comparator tcora tcrv0 interrupt request control tcsrv cmia cmib ovi internal data bus [legend] tcora: time constant register a tcorb: time constant register b tcntv: timer counter v tcsrv: timer control/status register v tcrv0: timer control register v0 tcrv1: timer control register v1 pss: prescaler s cmia: compare-match interrupt a cmib: compare-match interrupt b ovi: overflow interupt figure 11.1 block diagram of timer v 11.2 input/output pins table 11.1 shows the timer v pin configuration. table 11.1 pin configuration name abbreviation i/o function timer v output tmov output timer v waveform output timer v clock input tmciv input clock input to tcntv timer v reset input tmriv input external input to reset tcntv trigger input trgv input trigger input to initiate counting
section 11 timer v rev.5.00 nov. 02, 2005 page 139 of 418 rej09b0028-0500 11.3 register descriptions time v has the following registers. ? timer counter v (tcntv) ? timer constant register a (tcora) ? timer constant register b (tcorb) ? timer control register v0 (tcrv0) ? timer control/status register v (tcsrv) ? timer control register v1 (tcrv1) 11.3.1 timer counter v (tcntv) tcntv is an 8-bit up-counter. the clock source is selected by bits cks2 to cks0 in timer control register v0 (tcrv0). the tcntv value can be read and written by the cpu at any time. tcntv can be cleared by an external reset in put signal, or by compare match a or b. the clearing signal is selected by bits cclr1 and cclr0 in tcrv0. when tcntv overflows, ovf is set to 1 in timer control/status register v (tcsrv). tcntv is initialized to h'00. 11.3.2 time constant regist ers a and b (tcora, tcorb) tcora and tcorb have the same function. tcora and tcorb are 8-bit read/write registers. tcora and tcntv are compared at all times. when the tcora and tcntv contents match, cmfa is set to 1 in tcsrv. if cmiea is also se t to 1 in tcrv0, a cpu interrupt is requested. note that they must not be compared duri ng the t3 state of a tcora write cycle. timer output from the tmov pin can be controlled by the identifying signal (compare match a) and the settings of bits os3 to os0 in tcsrv. tcora and tcorb are initialized to h'ff.
section 11 timer v rev.5.00 nov. 02, 2005 page 140 of 418 rej09b0028-0500 11.3.3 timer control register v0 (tcrv0) tcrv0 selects the input clock signals of tcntv, specifies the clearing conditions of tcntv, and controls each interrupt request. bit bit name initial value r/w description 7 cmieb 0 r/w compare match interrupt enable b when this bit is set to 1, interrupt request from the cmfb bit in tcsrv is enabled. 6 cmiea 0 r/w compare match interrupt enable a when this bit is set to 1, interrupt request from the cmfa bit in tcsrv is enabled. 5 ovie 0 r/w timer overflow interrupt enable when this bit is set to 1, interrupt request from the ovf bit in tcsrv is enabled. 4 3 cclr1 cclr0 0 0 r/w r/w counter clear 1 and 0 these bits specify the clear ing conditions of tcntv. 00: clearing is disabled 01: cleared by compare match a 10: cleared by compare match b 11: cleared on the rising edge of the tmriv pin. the operation of tcntv after clearing depends on trge in tcrv1. 2 1 0 cks2 cks1 cks0 0 0 0 r/w r/w r/w clock select 2 to 0 these bits select clock signals to input to tcntv and the counting condition in combination with icks0 in tcrv1. refer to table 11.2.
section 11 timer v rev.5.00 nov. 02, 2005 page 141 of 418 rej09b0028-0500 table 11.2 clock signals to input to tcntv and counting conditions tcrv0 tcrv1 bit 2 bit 1 bit 0 bit 0 cks2 cks1 cks0 icks0 description 0 0 0 ? clock input prohibited 1 0 internal clock: counts on /4, falling edge 1 internal clock: counts on /8, falling edge 1 0 0 internal clock: counts on /16, falling edge 1 internal clock: counts on /32, falling edge 1 0 internal clock: counts on /64, falling edge 1 internal clock: counts on /128, falling edge 1 0 0 ? clock input prohibited 1 ? external clock: counts on rising edge 1 0 ? external clock: counts on falling edge 1 ? external clock: counts on rising and falling edge
section 11 timer v rev.5.00 nov. 02, 2005 page 142 of 418 rej09b0028-0500 11.3.4 timer control/st atus register v (tcsrv) tcsrv indicates the status flag and controls outputs by using a compare match. bit bit name initial value r/w description 7 cmfb 0 r/w compare match flag b setting condition: when the tcntv value matches the tcorb value clearing condition: after reading cmfb = 1, cleared by writing 0 to cmfb 6 cmfa 0 r/w compare match flag a setting condition: when the tcntv value matches the tcora value clearing condition: after reading cmfa = 1, cleared by writing 0 to cmfa 5 ovf 0 r/w timer overflow flag setting condition: when tcntv overflows from h'ff to h'00 clearing condition: after reading ovf = 1, cleared by writing 0 to ovf 4 ? 1 ? reserved this bit is always read as 1. 3 2 os3 os2 0 0 r/w r/w output select 3 and 2 these bits select an output method for the tmov pin by the compare match of tcorb and tcntv. 00: no change 01: 0 output 10: 1 output 11: output toggles 1 0 os1 os0 0 0 r/w r/w output select 1 and 0 these bits select an output method for the tmov pin by the compare match of tcora and tcntv. 00: no change 01: 0 output 10: 1 output 11: output toggles
section 11 timer v rev.5.00 nov. 02, 2005 page 143 of 418 rej09b0028-0500 os3 and os2 select the output level for compare match b. os1 and os0 select the output level for compare match a. the two output levels can be controlled independently. after a reset, the timer output is 0 until the first compare match. 11.3.5 timer control register v1 (tcrv1) tcrv1 selects the edge at the trgv pin, enab les trgv input, and selects the clock input to tcntv. bit bit name initial value r/w description 7 to 5 ? all 1 ? reserved these bits are always read as 1. 4 3 tveg1 tveg0 0 0 r/w r/w trgv input edge select these bits select the trgv input edge. 00: trgv trigger input is prohibited 01: rising edge is selected 10: falling edge is selected 11: rising and falling edges are both selected 2 trge 0 r/w tcnt starts counting up by the input of the edge which is selected by tveg1 and tveg0. 0: disables starting counting- up tcntv by the input of the trgv pin and halting counting-up tcntv when tcntv is cleared by a compare match. 1: enables starting counting- up tcntv by the input of the trgv pin and halting counting-up tcntv when tcntv is cleared by a compare match. 1 ? 1 ? reserved this bit is always read as 1. 0 icks0 0 r/w internal clock select 0 this bit selects clock sign als to input to tcntv in combination with cks2 to cks0 in tcrv0. refer to table 11.2.
section 11 timer v rev.5.00 nov. 02, 2005 page 144 of 418 rej09b0028-0500 11.4 operation 11.4.1 timer v operation 1. according to table 11.2, six internal/external clock signals output by prescaler s can be selected as the timer v operating clock signals . when the operating cl ock signal is selected, tcntv starts counting-up. figure 11.2 shows the count timing with an internal clock signal selected, and figure 11.3 shows the count timing with both edges of an external clock signal selected. 2. when tcntv overflows (changes from h'ff to h'00), the overflow flag (ovf) in tcrv0 will be set. the timing at this time is shown in fi gure 11.4. an interrupt request is sent to the cpu when ovie in tcrv0 is 1. 3. tcntv is constantly compared with tcora and tcorb. compare match flag a or b (cmfa or cmfb) is set to 1 when tcntv ma tches tcora or tcorb, respectively. the compare-match signal is generated in the last state in which the values match. figure 11.5 shows the timing. an interrupt request is generated for the cpu when cmiea or cmieb in tcrv0 is 1. 4. when a compare match a or b is generated, the tmov responds with the output value selected by bits os3 to os0 in tcsrv. figure 11.6 shows the timing when the output is toggled by compare match a. 5. when cclr1 or cclr0 in tcrv0 is 01 or 10, tcntv can be cleared by the corresponding compare match. figure 11.7 shows the timing. 6. when cclr1 or cclr0 in tcrv0 is 11, tcnt v can be cleared by the rising edge of the input of tmriv pin. a tmriv input pulse-width of at least 1.5 system clocks is necessary. figure 11.8 shows the timing. 7. when a counter-clearing source is generated with trge in tcrv1 set to 1, the counting-up is halted as soon as tcntv is cleared. tcntv resu mes counting-up when the edge selected by tveg1 or tveg0 in tcrv1 is input from the tgrv pin.
section 11 timer v rev.5.00 nov. 02, 2005 page 145 of 418 rej09b0028-0500 n ? 1 n + 1 n internal clock tcntv input clock tcntv figure 11.2 increment timi ng with internal clock n ? 1 n + 1 n tmciv (external clock input pin) tcntv input clock tcntv figure 11.3 increment timing with external clock h'ff h'00 tcntv overflow signal ovf figure 11.4 ovf set timing
section 11 timer v rev.5.00 nov. 02, 2005 page 146 of 418 rej09b0028-0500 n n n+1 tcntv tcora or tcorb compare match signal cmfa or cmfb figure 11.5 cmfa and cmfb set timing compare match a signal timer v output pin figure 11.6 tmov output timing n h'00 compare match a signal tcntv figure 11.7 clear ti ming by compare match
section 11 timer v rev.5.00 nov. 02, 2005 page 147 of 418 rej09b0028-0500 tmriv(external counter reset input pin ) tcntv reset signal tcntv n ? 1 n h'00 figure 11.8 clear ti ming by tmriv input
section 11 timer v rev.5.00 nov. 02, 2005 page 148 of 418 rej09b0028-0500 11.5 timer v application examples 11.5.1 pulse output with arbitrary duty cycle figure 11.9 shows an example of output of pulses with an arbitrary duty cycle. 1. set bits cclr1 and cclr0 in tcrv0 so that tcntv will be cleared by compare match with tcora. 2. set bits os3 to os0 in tcsrv so that the output will go to 1 at compare match with tcora and to 0 at compare match with tcorb. 3. set bits cks2 to cks0 in tcrv0 and bit icks0 in tcrv1 to select the desired clock source. 4. with these settings, a waveform is output without further software intervention, with a period determined by tcora and a pulse width determined by tcorb. counter cleared time tcntv value h'ff tcora tcorb h'00 tmov figure 11.9 pulse output example
section 11 timer v rev.5.00 nov. 02, 2005 page 149 of 418 rej09b0028-0500 11.5.2 pulse output with arbitrary pulse width and delay from trgv input the trigger function can be used to output a pulse with an arbitrary pulse width at an arbitrary delay from the trgv input, as shown in figure 11.10. to set up this output: 1. set bits cclr1 and cclr0 in tcrv0 so that tcntv will be cleared by compare match with tcorb. 2. set bits os3 to os0 in tcsrv so that the output will go to 1 at compare match with tcora and to 0 at compare match with tcorb. 3. set bits tveg1 and tveg0 in tcrv1 and set trge to select the falling edge of the trgv input. 4. set bits cks2 to cks0 in tcrv0 and bit icks0 in tcrv1 to select the desired clock source. 5. after these settings, a pulse waveform will be output without further software intervention, with a delay determined by tcora from the trgv input, and a pulse width determined by (tcorb ? tcora). counter cleared h'ff tcora tcorb h'00 trgv tmov compare match a compare match b clears tcntv and halts count-up compare match b clears tcntv and halts count-up compare match a tcntv value time figure 11.10 example of pulse ou tput synchronized to trgv input
section 11 timer v rev.5.00 nov. 02, 2005 page 150 of 418 rej09b0028-0500 11.6 usage notes the following types of contention or operation can occur in timer v operation. 1. writing to registers is performed in the t3 state of a tcntv write cycle. if a tcntv clear signal is generated in the t3 state of a tcntv write cycle, as shown in figure 11.11, clearing takes precedence and the write to the counter is not carried out. if counting-up is generated in the t3 state of a tcntv write cycle, writing takes precedence. 2. if a compare match is generated in the t3 st ate of a tcora or tcorb write cycle, the write to tcora or tcorb takes precedence and the compare match signal is inhibited. figure 11.12 shows the timing. 3. if compare matches a and b occur simultaneous ly, any conflict between the output selections for compare match a and compare match b is re solved by the following priority: toggle output > output 1 > output 0. 4. depending on the timing, tcntv may be incremented by a switch between different internal clock sources. when tcntv is internally clocked, an increment pulse is generated from the falling edge of an internal clock signal, that is divided system clock ( ). therefore, as shown in figure 11.3 the switch is from a high clock signal to a low clock signal, the switchover is seen as a falling edge, causing tcntv to incr ement. tcntv can also be incremented by a switch between internal and external clocks. address tcntv address tcntv write cycle by cpu internal write signal counter clear signal tcntv n h'00 t 1 t 2 t 3 figure 11.11 contention between tcntv write and clear
section 11 timer v rev.5.00 nov. 02, 2005 page 151 of 418 rej09b0028-0500 address tcora address internal write signal tcntv tcora n n n+1 m tcora write data inhibited t 1 t 2 t 3 tcora write cycle by cpu compare match signal figure 11.12 contention betwee n tcora write and compare match clock before switching clock after switching count clock tcntv n n+1 n+2 write to cks1 and cks0 figure 11.13 internal clock switching and tcntv operation
section 11 timer v rev.5.00 nov. 02, 2005 page 152 of 418 rej09b0028-0500
section 12 timer w tim08w0a_000020020200 rev.5.00 nov. 02, 2005 page 153 of 418 rej09b0028-0500 section 12 timer w the timer w has a 16-bit timer having output co mpare and input capture functions. the timer w can count external events and output pulses with an arbitrary duty cycle by compare match between the timer counter and four general registers. thus, it can be applied to various systems. 12.1 features ? selection of five counter clock sources: four internal clocks ( , /2, /4, and /8) and an external clock (external events can be counted) ? capability to process up to four pulse outputs or four pulse inputs ? four general registers: ? independently assignable output compare or input capture functions ? usable as two pairs of registers; one register of each pair operates as a buffer for the output compare or input capture register ? four selectable operating modes : ? waveform output by compare match selection of 0 output, 1 output, or toggle output ? input capture function rising edge, falling edge, or both edges ? counter clearing function counters can be cleared by compare match ? pwm mode up to three-phase pwm output can be provided with desired duty ratio. ? any initial timer output value can be set ? five interrupt sources four compare match/input capture interrupts and an overflow interrupt. table 12.1 summarizes the timer w functions, and figure 12.1 shows a block diagram of the timer w.
section 12 timer w rev.5.00 nov. 02, 2005 page 154 of 418 rej09b0028-0500 table 12.1 timer w functions input/output pins item counter ftioa ftiob ftioc ftiod count clock internal clocks: , /2, /4, /8 external clock: ftci general registers (output compare/input capture registers) period specified in gra gra grb grc (buffer register for gra in buffer mode) grd (buffer register for grb in buffer mode) counter clearing function gra compare match gra compare match ? ? ? initial output value setting function ? yes yes yes yes buffer function ? yes yes ? ? compare 0 ? yes yes yes yes match output 1 ? yes yes yes yes toggle ? yes yes yes yes input capture function ? yes yes yes yes pwm mode ? ? yes yes yes interrupt sources overflow compare match/input capture compare match/input capture compare match/input capture compare match/input capture
section 12 timer w rev.5.00 nov. 02, 2005 page 155 of 418 rej09b0028-0500 internal clock: external clock: ftci ftioa ftiob ftioc ftiod irrtw control logic clock selector comparator tcnt internal data bus bus interface [legend] tmrw: timer mode register w (8 bits) tcrw: timer control register w (8 bits) tierw: timer interrupt enable register w (8 bits) tsrw: timer status register w (8 bits) tior: timer i/o control register (8 bits) tcnt: timer counter (16 bits) gra: general register a (input capture/output compare register: 16 bits) grb: general register b (input capture/output compare register: 16 bits) grc: general register c (input capture/output compare register: 16 bits) grd: general register d (input capture/output compare register: 16 bits) irrtw: timer w interrupt request gra grb grc grd tmrw tcrw tierw tsrw tior /2 /4 /8 figure 12.1 timer w block diagram
section 12 timer w rev.5.00 nov. 02, 2005 page 156 of 418 rej09b0028-0500 12.2 input/output pins table 12.2 summarizes the timer w pins. table 12.2 pin configuration name abbreviation input/output function external clock input ftci input external clock input pin input capture/output compare a ftioa input/output output pin for gra output compare or input pin for gra input capture input capture/output compare b ftiob input/output output pi n for grb output compare, input pin for grb input capture, or pwm output pin in pwm mode input capture/output compare c ftioc input/output output pi n for grc output compare, input pin for grc input capture, or pwm output pin in pwm mode input capture/output compare d ftiod input/output output pi n for grd output compare, input pin for grd input capture, or pwm output pin in pwm mode 12.3 register descriptions the timer w has the following registers. ? timer mode register w (tmrw) ? timer control register w (tcrw) ? timer interrupt enable register w (tierw) ? timer status register w (tsrw) ? timer i/o control register 0 (tior0) ? timer i/o control register 1 (tior1) ? timer counter (tcnt) ? general register a (gra) ? general register b (grb) ? general register c (grc) ? general register d (grd)
section 12 timer w rev.5.00 nov. 02, 2005 page 157 of 418 rej09b0028-0500 12.3.1 timer mode register w (tmrw) tmrw selects the general register functions and the timer output mode. bit bit name initial value r/w description 7 cts 0 r/w counter start the counter operation is halted when this bit is 0, while it can be performed when this bit is 1. 6 ? 1 ? reserved this bit is always read as 1. 5 bufeb 0 r/w buffer operation b selects the grd function. 0: grd operates as an input capture/output compare register 1: grd operates as the buffer register for grb 4 bufea 0 r/w buffer operation a selects the grc function. 0: grc operates as an input capture/output compare register 1: grc operates as the buffer register for gra 3 ? 1 ? reserved this bit is always read as 1. 2 pwmd 0 r/w pwm mode d selects the output mode of the ftiod pin. 0: ftiod operates normally (output compare output) 1: pwm output 1 pwmc 0 r/w pwm mode c selects the output mode of the ftioc pin. 0: ftioc operates normally (output compare output) 1: pwm output 0 pwmb 0 r/w pwm mode b selects the output mode of the ftiob pin. 0: ftiob operates normally (output compare output) 1: pwm output
section 12 timer w rev.5.00 nov. 02, 2005 page 158 of 418 rej09b0028-0500 12.3.2 timer control register w (tcrw) tcrw selects the timer counter clock source, sel ects a clearing condition, and specifies the timer output levels. bit bit name initial value r/w description 7 cclr 0 r/w counter clear the tcnt value is cleared by compare match a when this bit is 1. when it is 0, tcnt operates as a free- running counter. 6 5 4 cks2 cks1 cks0 0 0 0 r/w r/w r/w clock select 2 to 0 select the tcnt clock source. 000: internal clock: counts on 001: internal clock: counts on /2 010: internal clock: counts on /4 011: internal clock: counts on /8 1xx: counts on rising edges of the external event (ftci) when the internal clock source ( ) is selected, subclock sources are counted in subactive and subsleep modes. 3 tod 0 r/w timer output level setting d sets the output value of t he ftiod pin until the first compare match d is generated. 0: output value is 0 * 1: output value is 1 * 2 toc 0 r/w timer output level setting c sets the output value of t he ftioc pin until the first compare match c is generated. 0: output value is 0 * 1: output value is 1 * 1 tob 0 r/w timer output level setting b sets the output value of t he ftiob pin until the first compare match b is generated. 0: output value is 0 * 1: output value is 1 *
section 12 timer w rev.5.00 nov. 02, 2005 page 159 of 418 rej09b0028-0500 bit bit name initial value r/w description 0 toa 0 r/w timer output level setting a sets the output value of t he ftioa pin until the first compare match a is generated. 0: output value is 0 * 1: output value is 1 * legend: x: don't care. note: * the change of the setting is immediat ely reflected in the output value. 12.3.3 timer interrupt en able register w (tierw) tierw controls the timer w interrupt request. bit bit name initial value r/w description 7 ovie 0 r/w timer overflow interrupt enable when this bit is set to 1, fovi interrupt requested by ovf flag in tsrw is enabled. 6 to 4 ? all 1 ? reserved these bits are always read as 1. 3 imied 0 r/w input capture/com pare match interrupt enable d when this bit is set to 1, imid interrupt requested by imfd flag in tsrw is enabled. 2 imiec 0 r/w input capture/com pare match interrupt enable c when this bit is set to 1, imic interrupt requested by imfc flag in tsrw is enabled. 1 imieb 0 r/w input capture/com pare match interrupt enable b when this bit is set to 1, imib interrupt requested by imfb flag in tsrw is enabled. 0 imiea 0 r/w input capture/com pare match interrupt enable a when this bit is set to 1, imia interrupt requested by imfa flag in tsrw is enabled.
section 12 timer w rev.5.00 nov. 02, 2005 page 160 of 418 rej09b0028-0500 12.3.4 timer status register w (tsrw) tsrw shows the status of interrupt requests. bit bit name initial value r/w description 7 ovf 0 r/w timer overflow flag [setting condition] when tcnt overflows from h'ffff to h'0000 [clearing condition] read ovf when ovf = 1, then write 0 in ovf 6 to 4 ? all 1 ? reserved these bits are always read as 1. 3 imfd 0 r/w input capt ure/compare match flag d [setting conditions] ? tcnt = grd when grd functions as an output compare register ? the tcnt value is transferred to grd by an input capture signal when grd functions as an input capture register [clearing condition] read imfd when imfd = 1, then write 0 in imfd 2 imfc 0 r/w input capt ure/compare match flag c [setting conditions] ? tcnt = grc when grc functions as an output compare register ? the tcnt value is transferred to grc by an input capture signal when grc functions as an input capture register [clearing condition] read imfc when imfc = 1, then write 0 in imfc
section 12 timer w rev.5.00 nov. 02, 2005 page 161 of 418 rej09b0028-0500 bit bit name initial value r/w description 1 imfb 0 r/w input capt ure/compare match flag b [setting conditions] ? tcnt = grb when grb functions as an output compare register ? the tcnt value is transferred to grb by an input capture signal when grb functions as an input capture register [clearing condition] read imfb when imfb = 1, then write 0 in imfb 0 imfa 0 r/w input capt ure/compare match flag a [setting conditions] ? tcnt = gra when gra functions as an output compare register ? the tcnt value is transferred to gra by an input capture signal when gra functions as an input capture register [clearing condition] read imfa when imfa = 1, then write 0 in imfa 12.3.5 timer i/o control register 0 (tior0) tior0 selects the functions of gra and grb, and specifies the functions of the ftioa and ftiob pins. bit bit name initial value r/w description 7 ? 1 ? reserved this bit is always read as 1. 6 iob2 0 r/w i/o control b2 selects the grb function. 0: grb functions as an output compare register 1: grb functions as an input capture register
section 12 timer w rev.5.00 nov. 02, 2005 page 162 of 418 rej09b0028-0500 bit bit name initial value r/w description 5 4 iob1 iob0 0 0 r/w r/w i/o control b1 and b0 when iob2 = 0, 00: no output at compare match 01: 0 output to the ftiob pin at grb compare match 10: 1 output to the ftiob pin at grb compare match 11: output toggles to the ftiob pin at grb compare match when iob2 = 1, 00: input capture at risi ng edge at the ftiob pin 01: input capture at fallin g edge at the ftiob pin 1x: input capture at rising and falling edges of the ftiob pin 3 ? 1 ? reserved this bit is always read as 1. 2 ioa2 0 r/w i/o control a2 selects the gra function. 0: gra functions as an output compare register 1: gra functions as an input capture register 1 0 ioa1 ioa0 0 0 r/w r/w i/o control a1 and a0 when ioa2 = 0, 00: no output at compare match 01: 0 output to the ftioa pin at gra compare match 10: 1 output to the ftioa pin at gra compare match 11: output toggles to the ftioa pin at gra compare match when ioa2 = 1, 00: input capture at risi ng edge of the ftioa pin 01: input capture at fallin g edge of the ftioa pin 1x: input capture at rising and falling edges of the ftioa pin legend: x: don't care.
section 12 timer w rev.5.00 nov. 02, 2005 page 163 of 418 rej09b0028-0500 12.3.6 timer i/o control register 1 (tior1) tior1 selects the functions of grc and grd, and specifies the functions of the ftioc and ftiod pins. bit bit name initial value r/w description 7 ? 1 ? reserved this bit is always read as 1. 6 iod2 0 r/w i/o control d2 selects the grd function. 0: grd functions as an output compare register 1: grd functions as an input capture register 5 4 iod1 iod0 0 0 r/w r/w i/o control d1 and d0 when iod2 = 0, 00: no output at compare match 01: 0 output to the ftiod pin at grd compare match 10: 1 output to the ftiod pin at grd compare match 11: output toggles to the ftiod pin at grd compare match when iod2 = 1, 00: input capture at risi ng edge at the ftiod pin 01: input capture at fallin g edge at the ftiod pin 1x: input capture at rising and falling edges at the ftiod pin 3 ? 1 ? reserved this bit is always read as 1. 2 ioc2 0 r/w i/o control c2 selects the grc function. 0: grc functions as an output compare register 1: grc functions as an input capture register
section 12 timer w rev.5.00 nov. 02, 2005 page 164 of 418 rej09b0028-0500 bit bit name initial value r/w description 1 0 ioc1 ioc0 0 0 r/w r/w i/o control c1 and c0 when ioc2 = 0, 00: no output at compare match 01: 0 output to the ftioc pin at grc compare match 10: 1 output to the ftioc pin at grc compare match 11: output toggles to the ftioc pin at grc compare match when ioc2 = 1, 00: input capture to grc at rising edge of the ftioc pin 01: input capture to grc at falling edge of the ftioc pin 1x: input capture to grc at rising and falling edges of the ftioc pin legend: x: don't care. 12.3.7 timer counter (tcnt) tcnt is a 16-bit readable/writable up-counter. th e clock source is selected by bits cks2 to cks0 in tcrw. tcnt can be cleared to h'0000 through a compare match with gra by setting the cclr in tcrw to 1. when tcnt overflows (changes from h'ffff to h'0000), the ovf flag in tsrw is set to 1. if ovie in tierw is set to 1 at this time, an interrupt request is generated. tcnt must always be read or writte n in 16-bit units; 8-bit access is not allowed. tcnt is initialized to h'0000 by a reset. 12.3.8 general registers a to d (gra to grd) each general register is a 16-bit readable/writable register that can function as either an output- compare register or an input-capture register. the function is selected by settings in tior0 and tior1. when a general register is used as an input-compare register, its value is constantly compared with the tcnt value. when the two values match (a compare match), the corresponding flag (imfa, imfb, imfc, or imfd) in tsrw is set to 1. an in terrupt request is generated at this time, when imiea, imieb, imiec, or imied is set to 1. compare match output can be selected in tior. when a general register is used as an input-captu re register, an external input-capture signal is detected and the current tcnt value is stored in the general register. the corresponding flag (imfa, imfb, imfc, or imfd) in tsrw is set to 1. if the corresponding interrupt-enable bit
section 12 timer w rev.5.00 nov. 02, 2005 page 165 of 418 rej09b0028-0500 (imiea, imieb, imiec, or imied) in tsrw is set to 1 at this time, an interrupt request is generated. the edge of the input-cap ture signal is selected in tior. grc and grd can be used as buffer registers of gra and grb, respectively, by setting bufea and bufeb in tmrw. for example, when gra is set as an output-compare register and grc is set as the buffer register for gra, the value in the buffer register grc is sent to gra whenever compare match a is generated. when gra is set as an input-capture register and grc is set as the buffer register for gra, the value in tcnt is transferred to gra and the valu e in the buffer register grc is transferred to gra whenever an input capture is generated. gra to grd must be written or read in 16-bit un its; 8-bit access is not a llowed. gra to grd are initialized to h'ffff by a reset. 12.4 operation the timer w has the following operating modes. ? normal operation ? pwm operation 12.4.1 normal operation tcnt performs free-running or periodic counting operations. after a reset, tcnt is set as a free- running counter. when the cts bit in tmrw is se t to 1, tcnt starts in crementing the count. when the count overflows from h'ffff to h'0000, the ovf flag in tsrw is set to 1. if the ovie in tierw is set to 1, an interrupt request is generated. figure 12.2 shows free-running counting.
section 12 timer w rev.5.00 nov. 02, 2005 page 166 of 418 rej09b0028-0500 tcnt value h'ffff h'0000 cts bit ovf time flag cleared by software figure 12.2 free-running counter operation periodic counting operation can be performed when gra is set as an output compare register and bit cclr in tcrw is set to 1. when the count matches gra, tcnt is cleared to h'0000, the imfa flag in tsrw is set to 1. if the correspond ing imiea bit in tierw is set to 1, an interrupt request is generated. tcnt continues counting from h'0000. figure 12.3 shows periodic counting. tcnt value gra h'0000 cts bit imfa time flag cleared by software figure 12.3 periodic counter operation by setting a general register as an output compare register, compare match a, b, c, or d can cause the output at the ftioa, ftiob, ftioc, or ftiod pin to output 0, output 1, or toggle. figure 12.4 shows an example of 0 and 1 output when tc nt operates as a free-running counter, 1 output is selected for compare match a, and 0 output is selected for compare match b. when signal is already at the selected output level, the sign al level does not change at compare match.
section 12 timer w rev.5.00 nov. 02, 2005 page 167 of 418 rej09b0028-0500 tcnt value h'ffff h'0000 ftioa ftiob time gra grb no change no change no change no change figure 12.4 0 and 1 output example (toa = 0, tob = 1) figure 12.5 shows an example of toggle output when tcnt operates as a free-running counter, and toggle output is selected for both compare match a and b. tcnt value h'ffff h'0000 ftioa ftiob time gra grb toggle output toggle output figure 12.5 toggle output example (toa = 0, tob = 1) figure 12.6 shows another example of toggle output when tcnt operates as a periodic counter, cleared by compare matc h a. toggle output is selected for both compare match a and b. tcnt value h'ffff h'0000 ftioa ftiob time gra grb toggle output toggle output counter cleared by compare match with gra figure 12.6 toggle output example (toa = 0, tob = 1)
section 12 timer w rev.5.00 nov. 02, 2005 page 168 of 418 rej09b0028-0500 the tcnt value can be captured into a general register (gra, grb, grc, or grd) when a signal level changes at an input-capture pin (ftioa, ftiob, ftioc, or ftiod). capture can take place on the rising edge, falli ng edge, or both edges. by usin g the input-capture function, the pulse width and periods can be measured. figure 12.7 shows an example of input capture when both edges of ftioa and the falling edge of ftiob are selected as capture edges. tcnt operates as a free-running counter. tcnt value h'ffff h'1000 h'0000 ftioa gra time h'aa55 h'55aa h'f000 h'1000 h'f000 h'55aa grb h'aa55 ftiob figure 12.7 input capture operating example figure 12.8 shows an example of buffer operation when the gra is set as an input-capture register and grc is set as the bu ffer register for gra. tcnt op erates as a free-running counter, and ftioa captures both rising and falling edge of the input signal. due to the buffer operation, the gra value is transferred to grc by input-cap ture a and the tcnt value is stored in gra.
section 12 timer w rev.5.00 nov. 02, 2005 page 169 of 418 rej09b0028-0500 tcnt value h'da91 h'0245 h'0000 grc time h'0245 ftioa gra h'5480 h'0245 h'ffff h'5480 h'5480 h'da91 figure 12.8 buffer operation example (input capture) 12.4.2 pwm operation in pwm mode, pwm waveforms are generated by using gra as the period register and grb, grc, and grd as duty registers. pwm waveforms are output from the ftiob, ftioc, and ftiod pins. up to three-phase pwm waveforms can be output. in pwm mode, a general register functions as an output compare register automatically. the out put level of each pin depends on the corresponding timer output level set bit (tob, toc, and tod) in tcrw. when tob is 1, the ftiob output goes to 1 at compare match a and to 0 at compare match b. when tob is 0, the ftiob output goes to 0 at compare match a and to 1 at compare match b. thus the compare match output level settings in tior0 and tior1 are ignored for the output pin set to pwm mode. if the same value is set in the cycle register and the duty register, the output does not change when a compare match occurs. figure 12.9 shows an example of operation in pwm mode. the output signals go to 1 and tcnt is cleared at compare match a, and the output sign als go to 0 at compare match b, c, and d (tob, toc, and tod = 1: initial output values are set to 1).
section 12 timer w rev.5.00 nov. 02, 2005 page 170 of 418 rej09b0028-0500 tcnt value gra grb grc h'0000 ftiob ftioc ftiod time grd counter cleared by compare match a figure 12.9 pwm mode example (1) figure 12.10 shows another example of operation in pwm mode. the output signals go to 0 and tcnt is cleared at compare match a, and the output signals go to 1 at compare match b, c, and d (tob, toc, and tod = 0: initial output values are set to 1). tcnt value gra grb grc h'0000 ftiob ftioc ftiod time grd counter cleared by compare match a figure 12.10 pwm mode example (2)
section 12 timer w rev.5.00 nov. 02, 2005 page 171 of 418 rej09b0028-0500 figure 12.11 shows an example of buffer opera tion when the ftiob pin is set to pwm mode and grd is set as the buffer register for grb. tc nt is cleared by compare match a, and ftiob outputs 1 at compare match b and 0 at compare match a. due to the buffer operation, the ftiob output level changes and the value of buffer register grd is transferred to grb whenever compare match b occurs. this proc edure is repeated every time compare match b occurs. tcnt value gra h'0000 grd time grb h'0200 h'0520 ftiob h'0200 h'0450 h'0520 h'0450 grb h'0450 h'0520 h'0200 figure 12.11 buffer operatio n example (output compare) figures 12.12 and 12.13 show examples of the output of pwm waveforms with duty cycles of 0% and 100%.
section 12 timer w rev.5.00 nov. 02, 2005 page 172 of 418 rej09b0028-0500 tcnt value gra h'0000 ftiob time grb duty 0% write to grb write to grb tcnt value gra h'0000 ftiob time grb duty 100% write to grb write to grb output does not change when cycle register and duty register compare matches occur simultaneously. tcnt value gra h'0000 ftiob time grb duty 100% write to grb write to grb write to grb output does not change when cycle register and duty register compare matches occur simultaneously. duty 0% write to grb figure 12.12 pwm mode example (tob, toc, and tod = 0: initial output values are set to 0)
section 12 timer w rev.5.00 nov. 02, 2005 page 173 of 418 rej09b0028-0500 tcnt value gra h'0000 ftiob time grb duty 100% write to grb tcnt value gra h'0000 ftiob time grb duty 0% write to grb write to grb output does not change when cycle register and duty register compare matches occur simultaneously. tcnt value gra h'0000 ftiob time grb duty 0% write to grb write to grb output does not change when cycle register and duty register compare matches occur simultaneously. duty 100% write to grb write to grb write to grb figure 12.13 pwm mode example (tob, toc, and tod = 1: initial output values are set to 1)
section 12 timer w rev.5.00 nov. 02, 2005 page 174 of 418 rej09b0028-0500 12.5 operation timing 12.5.1 tcnt count timing figure 12.14 shows the tcnt count timing when the internal clock source is selected. figure 12.15 shows the timing when the ex ternal clock source is selected. the pulse width of the external clock signal must be at least two system clock ( ) cycles; shorter pulses will not be counted correctly. tcnt tcnt input clock internal clock n n+1 n+2 rising edge figure 12.14 count timing for internal clock source tcnt tcnt input clock external clock nn+1 n+2 rising edge rising edge figure 12.15 count timing for external clock source 12.5.2 output comp are output timing the compare match signal is generated in the last state in which tcnt and gr match (when tcnt changes from the matching value to the next value). when the compare match signal is generated, the output value selected in tior is output at the compare match output pin (ftioa, ftiob, ftioc, or ftiod). when tcnt matches gr, the compare match signal is generated only after the next counter clock pulse is input.
section 12 timer w rev.5.00 nov. 02, 2005 page 175 of 418 rej09b0028-0500 figure 12.16 shows the output compare timing. gra to grd tcnt tcnt input clock n n n+1 compare match signal ftioa to ftiod figure 12.16 output compare output timing 12.5.3 input ca pture timing input capture on the rising edge, falling edge, or both edges can be selected through settings in tior0 and tior1. figure 12.17 shows the timing when the falling edge is selected. the pulse width of the input capture signal mu st be at least two system clock ( ) cycles; shorter pulses will not be detected correctly. tcnt input capture input n?1 n n+1 n+2 n gra to grd input capture signal figure 12.17 input capture input signal timing
section 12 timer w rev.5.00 nov. 02, 2005 page 176 of 418 rej09b0028-0500 12.5.4 timing of counter clearing by compare match figure 12.18 shows the timing when the counter is cleared by compare match a. when the gra value is n, the counter counts from 0 to n, and its cycle is n + 1. tcnt compare match signal gra n n h'0000 figure 12.18 timing of count er clearing by compare match 12.5.5 buffer operation timing figures 12.19 and 12.20 show the buffer operation timing. grc, grd compare match signal tcnt gra, grb n n+1 m m figure 12.19 buffer operat ion timing (compare match)
section 12 timer w rev.5.00 nov. 02, 2005 page 177 of 418 rej09b0028-0500 gra, grb tcnt input capture signal grc, grd n m m n+1 n n n+1 figure 12.20 buffer operation timing (input capture) 12.5.6 timing of imfa to imfd flag setting at compare match if a general register (gra, grb, grc, or grd) is used as an output compare register, the corresponding imfa, imfb, imfc, or imfd flag is set to 1 when tcnt matches the general register. the compare match signal is generated in the last state in which the values match (when tcnt is updated from the matching count to the next count). therefore, when tcnt matches a general register, the compare match signal is generated only after the next tcnt clock pulse is input. figure 12.21 shows the timing of the imfa to imfd flag setting at compare match. gra to grd tcnt tcnt input clock n n n+1 compare match signal imfa to imfd irrtw figure 12.21 timing of imfa to imfd flag setting at compare match
section 12 timer w rev.5.00 nov. 02, 2005 page 178 of 418 rej09b0028-0500 12.5.7 timing of imfa to im fd setting at input capture if a general register (gra, grb, grc, or grd) is used as an input capture register, the corresponding imfa, imfb, imfc, or imfd flag is set to 1 when an input capture occurs. figure 12.22 shows the timing of the imfa to imfd flag setting at input capture. gra to grd tcnt input capture signal n n imfa to imfd irrtw figure 12.22 timing of imfa to imfd flag setting at input capture 12.5.8 timing of st atus flag clearing when the cpu reads a status flag while it is set to 1, then writes 0 in the status flag, the status flag is cleared. figure 12.23 shows th e status flag clearing timing. imfa to imfd write signal address tsrw address irrtw tsrw write cycle t1 t2 figure 12.23 timing of status flag clearing by cpu
section 12 timer w rev.5.00 nov. 02, 2005 page 179 of 418 rej09b0028-0500 12.6 usage notes the following types of contention or operation can occur in timer w operation. 1. the pulse width of the input clock signal and the input capture signal must be at least two system clock ( ) cycles; shorter pulses will not be detected correctly. 2. writing to registers is performed in the t2 state of a tcnt write cycle. if counter clear signal occurs in the t2 state of a tcnt write cycle, clearing of the counter takes priority and the write is not performed, as shown in figure 12.24. if counting-up is generated in the tcnt write cycle to contend with the tcnt counting-up, writing takes precedence. 3. depending on the timing, tcnt may be incremented by a switch between different internal clock sources. when tcnt is internally clocked, an increment pulse is generated from the rising edge of an internal clock signal, that is divided system clock ( ). therefore, as shown in figure 12.25 the switch is from a low clock signal to a high clock signal, the switchover is seen as a rising edge, causing tcnt to increment. 4. if timer w enters module standby mode while an interrupt request is generated, the interrupt request cannot be cleared. before entering mo dule standby mode, disable interrupt requests. counter clear signal write signal address tcnt address tcnt tcnt write cycle t1 t2 n h'0000 figure 12.24 contention between tcnt write and clear
section 12 timer w rev.5.00 nov. 02, 2005 page 180 of 418 rej09b0028-0500 tcnt previous clock n n+1 n+2 n+3 new clock count clock the change in signal level at clock switching is assumed to be a rising edge, and tcnt increments the count. figure 12.25 internal clock switching and tcnt operation
section 12 timer w rev.5.00 nov. 02, 2005 page 181 of 418 rej09b0028-0500 5. the toa to tod bits in tcrw decide the value of the ftio pin, which is output until the first compare match occurs. once a compare matc h occurs and this comp are match changes the values of ftioa to ftiod output, the values of the ftioa to ftiod pin output and the values read from the toa to tod bits may differ. moreover, when the writing to tcrw and the generation of the compare match a to d occur at the same timing, the writing to tcrw has the priority. thus, output change due to the compare match is not reflected to the ftioa to ftiod pins. therefore, when bit manipulation instruction is used to write to tcrw, the values of the ftioa to ftiod pin output may result in an unexpected result. when tcrw is to be written to while compare match is opera ting, stop the counter once before accessing to tcrw, read the port 8 state to reflect the valu es of ftioa to ftiod output, to toa to tod, and then restart the counter. figure 12.26 sh ows an example when the compare match and the bit manipulation instruction to tcrw occur at the same timing. compare match signal b ftiob pin tcrw write signal set value bit tcrw 0 cclr 0 cks2 0 cks1 0 cks0 0 tod 1 toc 1 tob 0 765 43210 toa expected output remains high because the 1 writing to tob has priority tcrw has been set to h'06. compare match b and compare match c are used. the ftiob pin is in the 1 output state, and is set to the toggle output or the 0 output by compare match b. when bclr#2, @tcrw is executed to clear the toc bit (the ftioc signal is low) and compare match b occurs at the same timing as shown below, the h'02 writing to tcrw has priority and compare match b does not drive the ftiob signal lo w; the ftiob signal remains high. bclr#2, @tcrw (1) tcrw read operation: read h'06 (2) modify operation: modify h'06 to h'02 (3) write operation to tcrw: write h'02 figure 12.26 when compa re match and bit manipulation instruction to tcrw occur at the same timing
section 12 timer w rev.5.00 nov. 02, 2005 page 182 of 418 rej09b0028-0500
section 13 watchdog timer wdt0110a_000020020200 rev.5.00 nov. 02, 2005 page 183 of 418 rej09b0028-0500 section 13 watchdog timer the watchdog timer is an 8-bit timer that can gene rate an internal reset signal for this lsi if a system crash prevents the cpu from writing to th e timer counter, thus allowing it to overflow. the block diagram of the watchdog timer is shown in figure 13.1. internal reset signal pss tcwd tmwd tcsrwd internal data bus [legend] tcsrwd: timer control/status register wd tcwd: timer counter wd pss: prescaler s tmwd: timer mode register wd internal oscillator clk figure 13.1 block diagram of watchdog timer 13.1 features ? selectable from nine counter input clocks. eight clock sources ( /64, /128, /256, /512, /1024, /2048, /4096, and /8192) or the internal oscillator can be selected as the timer-c ounter clock. when the internal oscillator is selected, it can operate as the watc hdog timer in any operating mode. ? reset signal generated on counter overflow an overflow period of 1 to 256 times the selected clock can be set.
section 13 watchdog timer rev.5.00 nov. 02, 2005 page 184 of 418 rej09b0028-0500 13.2 register descriptions the watchdog timer has the following registers. ? timer control/status register wd (tcsrwd) ? timer counter wd (tcwd) ? timer mode register wd (tmwd) 13.2.1 timer control/stat us register wd (tcsrwd) tcsrwd performs the tcsrwd and tcwd writ e control. tcsrwd also controls the watchdog timer operation and indicates the operatin g state. tcsrwd must be rewritten by using the mov instruction. the bit manipulation instruction cannot be used to change the setting value. bit bit name initial value r/w description 7 b6wi 1 r/w bit 6 write inhibit the tcwe bit can be written only when the write value of the b6wi bit is 0. this bit is always read as 1. 6 tcwe 0 r/w timer counter wd write enable tcwd can be written when the tcwe bit is set to 1. when writing data to this bit, the value for bit 7 must be 0. 5 b4wi 1 r/w bit 4 write inhibit the tcsrwe bit can be written only when the write value of the b4wi bit is 0. this bit is always read as 1. 4 tcsrwe 0 r/w timer control/status register wd write enable the wdon and wrst bits can be written when the tcsrwe bit is set to 1. when writing data to this bit, the value for bit 5 must be 0. 3 b2wi 1 r/w bit 2 write inhibit this bit can be written to the wdon bit only when the write value of the b2wi bit is 0. this bit is always read as 1.
section 13 watchdog timer rev.5.00 nov. 02, 2005 page 185 of 418 rej09b0028-0500 bit bit name initial value r/w description 2 wdon 0 r/w watchdog timer on tcwd starts counting up when wdon is set to 1 and halts when wdon is cleared to 0. [setting condition] when 1 is written to the wdon bit while writing 0 to the b2wi bit when the tcsrwe bit=1 [clearing conditions] ? reset by res pin ? when 0 is written to the wdon bit while writing 0 to the b2wi when the tcsrwe bit=1 1 b0wi 1 r/w bit 0 write inhibit this bit can be written to the wrst bit only when the write value of the b0wi bit is 0. this bit is always read as 1. 0 wrst 0 r/w watchdog timer reset [setting condition] when tcwd overflows and an internal reset signal is generated [clearing conditions] ? reset by res pin ? when 0 is written to the wrst bit while writing 0 to the b0wi bit when the tcsrwe bit=1 13.2.2 timer coun ter wd (tcwd) tcwd is an 8-bit readable/writable up-counter. when tcwd overflows from h'ff to h'00, the internal reset signal is generated and the wrst bit in tcsrwd is set to 1. tcwd is initialized to h'00.
section 13 watchdog timer rev.5.00 nov. 02, 2005 page 186 of 418 rej09b0028-0500 13.2.3 timer mode register wd (tmwd) tmwd selects the input clock. bit bit name initial value r/w description 7 to 4 ? all 1 ? reserved these bits are always read as 1. 3 2 1 0 cks3 cks2 cks1 cks0 1 1 1 1 r/w r/w r/w r/w clock select 3 to 0 select the clock to be input to tcwd. 1000: internal clock: counts on /64 1001: internal clock: counts on /128 1010: internal clock: counts on /256 1011: internal clock: counts on /512 1100: internal clock: counts on /1024 1101: internal clock: counts on /2048 1110: internal clock: counts on /4096 1111: internal clock: counts on 8192 0xxx: internal oscillator for the internal oscillator overflow periods, see section 21, electrical characteristics. legend: x: don't care.
section 13 watchdog timer rev.5.00 nov. 02, 2005 page 187 of 418 rej09b0028-0500 13.3 operation the watchdog timer is provided with an 8-bit counter. if 1 is written to wdon while writing 0 to b2wi when the tcsrwe bit in tcsrwd is set to 1, tcwd begins counting up. (to operate the watchdog timer, two write accesses to tcsrwd are required.) when a clock pulse is input after the tcwd count value has reached h'ff, the watchdog timer overflows and an internal reset signal is generated. the internal reset signal is output for a period of 256 osc clock cycles. tcwd is a writable counter, and when a value is set in tc wd, the count-up starts from that value. an overflow period in the range of 1 to 256 input cl ock cycles can therefore be set, according to the tcwd set value. figure 13.2 shows an example of watchdog timer operation. example: with 30ms overflow period when = 4 mhz 4 10 6 30 10 ?3 = 14.6 8192 tcwd overflow h'ff h'00 internal reset signal h'f1 tcwd count value h'f1 written to tcwd h'f1 written to tcwd reset generated start 256 osc clock cycles therefore, 256 ? 15 = 241 (h'f1) is set in tcw. figure 13.2 watchdog timer operation example
section 13 watchdog timer rev.5.00 nov. 02, 2005 page 188 of 418 rej09b0028-0500
section 14 serial communication interface 3 (sci3) sci0010a_000020020200 rev.5.00 nov. 02, 2005 page 189 of 418 rej09b0028-0500 section 14 serial communi cation interface 3 (sci3) serial communication interface 3 (sci3) can handle both asynchronous and clocked synchronous serial communication. in the asyn chronous method, serial data communication can be carried out using standard asynchronous communication chips such as a universal asynchronous receiver/transmitter (uart) or an asynchronou s communication interface adapter (acia). a function is also provided for serial commun ication between processors (multiprocessor communication function). figure 14.1 shows a block diagram of the sci3. 14.1 features ? choice of asynchronous or clocked synchronous serial communication mode ? full-duplex communication capability the transmitter and receiver are mutually independ ent, enabling transmission and reception to be executed simultaneously. double-buffering is used in both the transmitter and the receiver, enabling continuous transmission and continuous reception of serial data. ? on-chip baud rate generator allows any bit rate to be selected ? external clock or on-chip baud rate generator can be selected as a transfer clock source. ? six interrupt sources transmit-end, transmit-data-empty , receive-data-full, ove rrun error, framing error, and parity error. asynchronous mode ? data length: 7 or 8 bits ? stop bit length: 1 or 2 bits ? parity: even, odd, or none ? receive error detection: parity , overrun, and framing errors ? break detection: break can be detected by read ing the rxd pin level directly in the case of a framing error clocked synchronous mode ? data length: 8 bits ? receive error detection: overrun errors detected
section 14 serial communication interface 3 (sci3) rev.5.00 nov. 02, 2005 page 190 of 418 rej09b0028-0500 clock txd rxd sck 3 brr smr scr3 ssr tdr rdr tsr rsr transmit/receive control circuit internal data bus [legend] rsr: rdr: tsr: tdr: smr: scr3: ssr: brr: brc: receive shift register receive data register transmit shift register transmit data register serial mode register serial control register 3 serial status register bit rate register bit rate counter interrupt request (tei, txi, rxi, eri) internal clock ( /64, /16, /4, ) external clock brc baud rate generator figure 14.1 block diagram of sci3
section 14 serial communication interface 3 (sci3) rev.5.00 nov. 02, 2005 page 191 of 418 rej09b0028-0500 14.2 input/output pins table 14.1 shows the sci3 pin configuration. table 14.1 pin configuration pin name abbreviation i/o function sci3 clock sck3 i/o sc i3 clock input/output sci3 receive data input rxd i nput sci3 receive data input sci3 transmit data output txd output sci3 transmit data output 14.3 register descriptions the sci3 has the following registers. ? receive shift register (rsr) ? receive data register (rdr) ? transmit shift register (tsr) ? transmit data register (tdr) ? serial mode register (smr) ? serial control register 3 (scr3) ? serial status register (ssr) ? bit rate register (brr)
section 14 serial communication interface 3 (sci3) rev.5.00 nov. 02, 2005 page 192 of 418 rej09b0028-0500 14.3.1 receive shi ft register (rsr) rsr is a shift register that is us ed to receive serial data input fr om the rxd pin and convert it into parallel data. when one byte of data has been r eceived, it is transferred to rdr automatically. rsr cannot be directly accessed by the cpu. 14.3.2 receive data register (rdr) rdr is an 8-bit register that stores received data . when the sci3 has received one byte of serial data, it transfers the received serial data from rsr to rdr, where it is stor ed. after this, rsr is receive-enabled. as rsr and rdr function as a d ouble buffer in this way, continuous receive operations are possible. after confirming that the rdrf bit in ssr is set to 1, read rdr only once. rdr cannot be written to by the cpu. rdr is initialized to h'00. 14.3.3 transmit shift register (tsr) tsr is a shift register that transmits serial data. to perform serial data transmission, the sci3 first transfers transmit data fr om tdr to tsr automatically, then sends the data that starts from the lsb to the txd pin . tsr cannot be directly accessed by the cpu. 14.3.4 transmit data register (tdr) tdr is an 8-bit register that stores data for transmission. when the sc i3 detects that tsr is empty, it transfers the tr ansmit data written in tdr to tsr an d starts transmission. the double- buffered structure of tdr and tsr enables continuous serial transmission. if the next transmit data has already been written to tdr during transm ission of one-frame data, the sci3 transfers the written data to tsr to continue transmission. to achieve reliable serial transmission, write transmit data to tdr only once after confirming th at the tdre bit in ssr is set to 1. tdr is initialized to h'ff.
section 14 serial communication interface 3 (sci3) rev.5.00 nov. 02, 2005 page 193 of 418 rej09b0028-0500 14.3.5 serial mode register (smr) smr is used to set the sci3?s serial transfer fo rmat and select the on-chip baud rate generator clock source. bit bit name initial value r/w description 7 com 0 r/w communication mode 0: asynchronous mode 1: clocked synchronous mode 6 chr 0 r/w character length (enabled only in asynchronous mode) 0: selects 8 bits as the data length. 1: selects 7 bits as the data length. 5 pe 0 r/w parity enable (enabled only in asynchronous mode) when this bit is set to 1, the parity bit is added to transmit data before transmission, and the parity bit is checked in reception. 4 pm 0 r/w parity mode (enabled only when the pe bit is 1 in asynchronous mode) 0: selects even parity. 1: selects odd parity. 3 stop 0 r/w stop bit length (enabled only in asynchronous mode) selects the stop bit length in transmission. 0: 1 stop bit 1: 2 stop bits for reception, only the first stop bit is checked, regardless of the value in the bit. if the second stop bit is 0, it is treated as the start bit of the next transmit character. 2 mp 0 r/w multiprocessor mode when this bit is set to 1, the multiprocessor communication function is enabled. the pe bit and pm bit settings are invalid. in clocked synchronous mode, this bit should be cleared to 0.
section 14 serial communication interface 3 (sci3) rev.5.00 nov. 02, 2005 page 194 of 418 rej09b0028-0500 bit bit name initial value r/w description 1 0 cks1 cks0 0 0 r/w r/w clock select 0 and 1 these bits select the clock source for the on-chip baud rate generator. 00: clock (n = 0) 01: /4 clock (n = 1) 10: /16 clock (n = 2) 11: /64 clock (n = 3) for the relationship between the bit rate register setting and the baud rate, see section 14.3.8, bit rate register (brr). n is the decimal represent ation of the value of n in brr (see section 14.3.8, bit rate register (brr)). 14.3.6 serial control register 3 (scr3) scr3 is a register that enables or disables sci3 transfer operations and interrupt requests, and is also used to select the transfer clock source. for details on interrupt requests, refer to section 14.7, interrupts. bit bit name initial value r/w description 7 tie 0 r/w transmit interrupt enable when this bit is set to 1, the txi interrupt request is enabled. 6 rie 0 r/w receive interrupt enable when this bit is set to 1, rxi and eri interrupt requests are enabled. 5 te 0 r/w transmit enable when this bit is set to 1, transmission is enabled. 4 re 0 r/w receive enable when this bit is set to 1, reception is enabled.
section 14 serial communication interface 3 (sci3) rev.5.00 nov. 02, 2005 page 195 of 418 rej09b0028-0500 bit bit name initial value r/w description 3 mpie 0 r/w multiprocessor interrupt enable (enabled only when the mp bit in smr is 1 in asynchronous mode) when this bit is set to 1, receive data in which the multiprocessor bit is 0 is skipped, and setting of the rdrf, fer, and oer status flags in ssr is prohibited. on receiving data in which the multiprocessor bit is 1, this bit is automatically cleared and normal reception is resumed. for details, re fer to section 14.6, multiprocessor communi cation function. 2 teie 0 r/w transmit end interrupt enable when this bit is set to 1, the tei interrupt request is enabled. 1 0 cke1 cke0 0 0 r/w r/w clock enable 0 and 1 selects the clock source. asynchronous mode: 00: internal baud rate generator 01: internal baud rate generator outputs a clock of the same frequency as the bit rate from the sck3 pin. 10: external clock inputs a clock with a frequency 16 times the bit rate from the sck3 pin. 11: reserved clocked synchronous mode: 00: internal clock (sck3 pin functions as clock output) 01: reserved 10: external clock (sck3 pin functions as clock input) 11: reserved
section 14 serial communication interface 3 (sci3) rev.5.00 nov. 02, 2005 page 196 of 418 rej09b0028-0500 14.3.7 serial status register (ssr) ssr is a register containing status flags of the sci3 and multiprocessor bits for transfer. 1 cannot be written to flags tdre, rdrf, oer, per, and fer; they can only be cleared. bit bit name initial value r/w description 7 tdre 1 r/w transmit data register empty displays whether tdr contains transmit data. [setting conditions] ? when the te bit in scr3 is 0 ? when data is transferred from tdr to tsr [clearing conditions] ? when 0 is written to tdre after reading tdre = 1 ? when the transmit data is written to tdr 6 rdrf 0 r/w receive data register full indicates that the received data is stored in rdr. [setting condition] ? when serial reception ends normally and receive data is transferred from rsr to rdr [clearing conditions] ? when 0 is written to rdrf after reading rdrf = 1 ? when data is read from rdr 5 oer 0 r/w overrun error [setting condition] ? when an overrun error occurs in reception [clearing condition] ? when 0 is written to oer after reading oer = 1 4 fer 0 r/w framing error [setting condition] ? when a framing error occurs in reception [clearing condition] ? when 0 is written to fer after reading fer = 1
section 14 serial communication interface 3 (sci3) rev.5.00 nov. 02, 2005 page 197 of 418 rej09b0028-0500 bit bit name initial value r/w description 3 per 0 r/w parity error [setting condition] ? when a parity error is generated during reception [clearing condition] ? when 0 is written to per after reading per = 1 2 tend 1 r transmit end [setting conditions] ? when the te bit in scr3 is 0 ? when tdre = 1 at transmission of the last bit of a 1- byte serial transmit character [clearing conditions] ? when 0 is written to tend after reading tend = 1 ? when the transmit data is written to tdr 1 mpbr 0 r multiprocessor bit receive mpbr stores the multiprocessor bit in the receive character data. when the re bit in scr3 is cleared to 0, its previous state is retained. 0 mpbt 0 r/w multiprocessor bit transfer mpbt stores the multiprocessor bit to be added to the transmit character data.
section 14 serial communication interface 3 (sci3) rev.5.00 nov. 02, 2005 page 198 of 418 rej09b0028-0500 14.3.8 bit rate register (brr) brr is an 8-bit register that adjusts the bit rate. the initial value of brr is h'ff. table 14.2 shows the relationship between the n setting in brr and the n setting in bits cks1 and cks0 of smr in asynchronous mode. table 14.3 show s the maximum bit rate for each frequency in asynchronous mode. the values shown in both ta bles 14.2 and 14.3 are values in active (high- speed) mode. table 14.4 shows the relationship between the n setting in brr and the n setting in bits cks1 and cks0 in smr in clocked synchronous mode. the values shown in table 14.4 are values in active (high-speed) mode. the n setting in brr and error for other operating frequencies and bit rates can be obtained by the following formulas: [asynchronous mode] n = 64 2 2n?1 b 10 6 ? 1 error (%) = ? 1 100 ? ? ? ? ? ? 10 6 (n + 1) b 64 2 2n?1 [clocked synchronous mode] n = 8 2 2n?1 b 10 6 ? 1 note: b: bit rate (bit/s) n: brr setting for baud rate generator (0 n 255) : operating frequency (mhz) n: cks1 and cks0 setting for smr (0 n 3)
section 14 serial communication interface 3 (sci3) rev.5.00 nov. 02, 2005 page 199 of 418 rej09b0028-0500 table 14.2 examples of brr settings for various bit rates (asynchronous mode) (1) operating frequency (mhz) 2 2.097152 2.4576 3 bit rate (bits/s) n n error (%) n n error (%) n n error (%) n n error (%) 110 1 141 0.03 1 148 ?0.04 1 174 ?0.26 1 212 0.03 150 1 103 0.16 1 108 0.21 1 127 0.00 1 155 0.16 300 0 207 0.16 0 217 0.21 0 255 0.00 1 77 0.16 600 0 103 0.16 0 108 0.21 0 127 0.00 0 155 0.16 1200 0 51 0.16 0 54 ?0.70 0 63 0.00 0 77 0.16 2400 0 25 0.16 0 26 1.14 0 31 0.00 0 38 0.16 4800 0 12 0.16 0 13 ?2.48 0 15 0.00 0 19 ?2.34 9600 0 6 ?6.99 0 6 ?2.48 0 7 0.00 0 9 ?2.34 19200 0 2 8.51 0 2 13.78 0 3 0.00 0 4 ?2.34 31250 0 1 0.00 0 1 4.86 0 1 22.88 0 2 0.00 38400 0 1 ?18.62 0 1 ?14.67 0 1 0.00 ? ? ? legend: ? : a setting is available but error occurs operating frequency (mhz) 3.6864 4 4.9152 5 bit rate (bits/s) n n error (%) n n error (%) n n error (%) n n error (%) 110 2 64 0.70 2 70 0.03 2 86 0.31 2 88 ?0.25 150 1 191 0.00 1 207 0.16 1 255 0.00 2 64 0.16 300 1 95 0.00 1 103 0.16 1 127 0.00 1 129 0.16 600 0 191 0.00 0 207 0.16 0 255 0.00 1 64 0.16 1200 0 95 0.00 0 103 0.16 0 127 0.00 0 129 0.16 2400 0 47 0.00 0 51 0.16 0 63 0.00 0 64 0.16 4800 0 23 0.00 0 25 0.16 0 31 0.00 0 32 ?1.36 9600 0 11 0.00 0 12 0.16 0 15 0.00 0 15 1.73 19200 0 5 0.00 0 6 ?6.99 0 7 0.00 0 7 1.73 31250 ? ? ? 0 3 0.00 0 4 ?1.70 0 4 0.00 38400 0 2 0.00 0 2 8.51 0 3 0.00 0 3 1.73
section 14 serial communication interface 3 (sci3) rev.5.00 nov. 02, 2005 page 200 of 418 rej09b0028-0500 table 14.2 examples of brr settings for various bit rates (asynchronous mode) (2) operating frequency (mhz) 6 6.144 7.3728 8 bit rate (bit/s) n n error (%) n n error (%) n n error (%) n n error (%) 110 2 106 ?0.44 2 108 0.08 2 130 ?0.07 2 141 0.03 150 2 77 0.16 2 79 0.00 2 95 0.00 2 103 0.16 300 1 155 0.16 1 159 0.00 1 191 0.00 1 207 0.16 600 1 77 0.16 1 79 0.00 1 95 0.00 1 103 0.16 1200 0 155 0.16 0 159 0.00 0 191 0.00 0 207 0.16 2400 0 77 0.16 0 79 0.00 0 95 0.00 0 103 0.16 4800 0 38 0.16 0 39 0.00 0 47 0.00 0 51 0.16 9600 0 19 ?2.34 0 19 0.00 0 23 0.00 0 25 0.16 19200 0 9 ?2.34 0 9 0.00 0 11 0.00 0 12 0.16 31250 0 5 0.00 0 5 2.40 0 6 5.33 0 7 0.00 38400 0 4 ?2.34 0 4 0.00 0 5 0.00 0 6 -6.99 operating frequency (mhz) 9.8304 10 12 12.888 bit rate (bit/s) n n error (%) n n error (%) n n error (%) n n error (%) 110 2 174 ?0.26 2 177 ?0.25 2 212 0.03 2 217 0.08 150 2 127 0.00 2 129 0.16 2 155 0.16 2 159 0.00 300 1 255 0.00 2 64 0.16 2 77 0.16 2 79 0.00 600 1 127 0.00 1 129 0.16 1 155 0.16 1 159 0.00 1200 0 255 0.00 1 64 0.16 1 77 0.16 1 79 0.00 2400 0 127 0.00 0 129 0.16 0 155 0.16 0 159 0.00 4800 0 63 0.00 0 64 0.16 0 77 0.16 0 79 0.00 9600 0 31 0.00 0 32 ?1.36 0 38 0.16 0 39 0.00 19200 0 15 0.00 0 15 1.73 0 19 ?2.34 0 19 0.00 31250 0 9 ?1.70 0 9 0.00 0 11 0.00 0 11 2.40 38400 0 7 0.00 0 7 1.73 0 9 ?2.34 0 9 0.00
section 14 serial communication interface 3 (sci3) rev.5.00 nov. 02, 2005 page 201 of 418 rej09b0028-0500 table 14.2 examples of brr settings for various bit rates (asynchronous mode) (3) operating frequency (mhz) 14 14.7456 16 bit rate (bit/s) n n error (%) n n error (%) n n error (%) 110 2 248 ?0.17 3 64 0.70 3 70 0.03 150 2 181 0.16 2 191 0.00 2 207 0.16 300 2 90 0.16 2 95 0.00 2 103 0.16 600 1 181 0.16 1 191 0.00 1 207 0.16 1200 1 90 0.16 1 95 0.00 1 103 0.16 2400 0 181 0.16 0 191 0.00 0 207 0.16 4800 0 90 0.16 0 95 0.00 0 103 0.16 9600 0 45 ?0.93 0 47 0.00 0 51 0.16 19200 0 22 ?0.93 0 23 0.00 0 25 0.16 31250 0 13 0.00 0 14 ?1.70 0 15 0.00 38400 ? ? ? 0 11 0.00 0 12 0.16 operating frequency (mhz) 18 20 bit rate (bit/s) n n error (%) n n error (%) 110 3 79 ?0.12 3 88 ?0.25 150 2 233 0.16 3 64 0.16 300 2 116 0.16 2 129 0.16 600 1 233 0.16 2 64 0.16 1200 1 116 0.16 1 129 0.16 2400 0 233 0.16 1 64 0.16 4800 0 116 0.16 0 129 0.16 9600 0 58 ?0.96 0 64 0.16 19200 0 28 1.02 0 32 ?1.36 31250 0 17 0.00 0 19 0.00 38400 0 14 ?2.34 0 15 1.73 legend: ?: a setting is available but error occurs.
section 14 serial communication interface 3 (sci3) rev.5.00 nov. 02, 2005 page 202 of 418 rej09b0028-0500 table 14.3 maximum bit rate for ea ch frequency (asynchronous mode) (mhz) maximum bit rate (bit/s) n n (mhz) maximum bit rate (bit/s) n n 2 62500 0 0 8 250000 0 0 2.097152 65536 0 0 9.8304 307200 0 0 2.4576 76800 0 0 10 312500 0 0 3 93750 0 0 12 375000 0 0 3.6864 115200 0 0 12.288 384000 0 0 4 125000 0 0 14 437500 0 0 4.9152 153600 0 0 14.7456 460800 0 0 5 156250 0 0 16 500000 0 0 6 187500 0 0 17.2032 537600 0 0 6.144 192000 0 0 18 562500 0 0 7.3728 230400 0 0 20 625000 0 0
section 14 serial communication interface 3 (sci3) rev.5.00 nov. 02, 2005 page 203 of 418 rej09b0028-0500 table 14.4 examples of bbr setting for va rious bit rates (clocked synchronous mode) (1) operating frequency (mhz) 2 4 8 10 16 bit rate (bit/s) n n n n n n n n n n 110 3 70 ? ? ? ? ? ? 250 2 124 2 249 3 124 ? ? 3 249 500 1 249 2 124 2 249 ? ? 3 124 1k 1 124 1 249 2 124 ? ? 2 249 2.5k 0 199 1 99 1 199 1 249 2 99 5k 0 99 0 199 1 99 1 124 1 199 10k 0 49 0 99 0 199 0 249 1 99 25k 0 19 0 39 0 79 0 99 0 159 50k 0 9 0 19 0 39 0 49 0 79 100k 0 4 0 9 0 19 0 24 0 39 250k 0 1 0 3 0 7 0 9 0 15 500k 0 0 * 0 1 0 3 0 4 0 7 1m 0 0 * 0 1 ? ? 0 3 2m 0 0 * ? ? 0 1 2.5m 0 0 * ? ? 4m 0 0 * legend: blank : no setting is available. ? : a setting is available but error occurs. * : continuous transfer is not possible.
section 14 serial communication interface 3 (sci3) rev.5.00 nov. 02, 2005 page 204 of 418 rej09b0028-0500 table 14.4 examples of brr settings for va rious bit rates (clocked synchronous mode) (2) operating frequency (mhz) 18 20 bit rate (bit/s) n n n n 110 ? ? ? ? 250 ? ? ? ? 500 3 140 3 155 1k 3 69 3 77 2.5k 2 112 2 124 5k 1 224 1 249 10k 1 112 1 124 25k 0 179 0 199 50k 0 89 0 99 100k 0 44 0 49 250k 0 17 0 19 500k 0 8 0 9 1m 0 4 0 4 2m ? ? ? ? 2.5m ? ? 0 1 4m ? ? ? ? legend: blank : no setting is available. ? : a setting is available but error occurs. * : continuous transfer is not possible.
section 14 serial communication interface 3 (sci3) rev.5.00 nov. 02, 2005 page 205 of 418 rej09b0028-0500 14.4 operation in asynchronous mode figure 14.2 shows the general format for asynchronous serial communication. one frame consists of a start bit (low level), followed by data (in lsb-first order), a parity bit (high or low level), and finally stop bits (high level). inside the sci3, the transmitter and receive r are independent units, enabling full duplex. both the tr ansmitter and the receiver also ha ve a double-buffered structure, so data can be read or written during transmission or reception, enabling continuous data transfer. lsb start bit msb mark state stop bit transmit/receive data 1 serial data parity bit 1 bit 1 or 2 bits 7 or 8 bits 1 bit, or none one unit of transfer data (character or frame) figure 14.2 data format in asynchronous communication 14.4.1 clock either an internal clock generated by the on-chip baud rate generator or an external clock input at the sck3 pin can be selected as the sci3?s serial clock source, according to the setting of the com bit in smr and the cke0 and cke1 bits in scr3. when an external clock is input at the sck3 pin, the clock frequency should be 16 times the bit rate used. when the sci3 is operated on an internal clock, the clock can be output from the sck3 pin. the frequency of the clock output in this case is equal to the bit rate, and the phase is such that the rising edge of the clock is in the middle of the transmit data, as shown in figure 14.3. 0 1 character (frame) d0 d1 d2 d3 d4 d5 d6 d7 0/1 11 clock serial data figure 14.3 relationship between output clock and transfer data phase (asynchronous mode) (example with 8-bit data, parity, two stop bits)
section 14 serial communication interface 3 (sci3) rev.5.00 nov. 02, 2005 page 206 of 418 rej09b0028-0500 14.4.2 sci3 initialization follow the flowchart as shown in figure 14.4 to initialize the sci3. when the te bit is cleared to 0, the tdre flag is set to 1. note that clearing the re bit to 0 does not initialize the contents of the rdrf, per, fer, and oer flags, or the contents of rdr. when the external clock is used in asynchronous mode, the clock must be supplied even during initialization. wait start initialization set data transfer format in smr [1] set cke1 and cke0 bits in scr3 no yes set value in brr clear te and re bits in scr3 to 0 [2] [3] set te and re bits in scr3 to 1, and set rie, tie, teie, and mpie bits. for transmit (te=1), also set the txd bit in pmr1. [4] 1-bit interval elapsed? [1] set the clock selection in scr3. be sure to clear bits rie, tie, teie, and mpie, and bits te and re, to 0. when the clock output is selected in asynchronous mode, clock is output immediately after cke1 and cke0 settings are made. when the clock output is selected at reception in clocked synchronous mode, clock is output immediately after cke1, cke0, and re are set to 1. [2] set the data transfer format in smr. [3] write a value corresponding to the bit rate to brr. not necessary if an external clock is used. [4] wait at least one bit interval, then set the te bit or re bit in scr3 to 1. re settings enable the rxd pin to be used. for transmission, set the txd bit in pmr1 to 1 to enable the txd output pin to be used. also set the rie, tie, teie, and mpie bits, depending on whether interrupts are required. in asynchronous mode, the bits are marked at transmission and idled at reception to wait for the start bit. figure 14.4 sample sci3 initialization flowchart
section 14 serial communication interface 3 (sci3) rev.5.00 nov. 02, 2005 page 207 of 418 rej09b0028-0500 14.4.3 data transmission figure 14.5 shows an example of operation for transmission in asynchronous mode. in transmission, the sci3 operates as described below. 1. the sci3 monitors the tdre flag in ssr. if the flag is cleared to 0, th e sci3 recognizes that data has been written to tdr, and tr ansfers the data from tdr to tsr. 2. after transferring data from tdr to tsr, the sci3 sets the tdre flag to 1 and starts transmission. if the tie bit is set to 1 at th is time, a txi interrupt request is generated. continuous transmission is possible because the txi interrupt routine writes next transmit data to tdr before transmission of the current transmit data has been completed. 3. the sci3 checks the tdre flag at the timing for sending the stop bit. 4. if the tdre flag is 0, the data is transferred from tdr to tsr, the stop bit is sent, and then serial transmission of the next frame is started. 5. if the tdre flag is 1, the tend flag in ssr is set to 1, the stop bit is sent, and then the ?mark state? is entered, in which 1 is output. if the teie bit in scr3 is set to 1 at this time, a tei interrupt request is generated. 6. figure 14.6 shows a sample flowchart for transmission in asynchronous mode. 1 frame start bit start bit transmit data transmit data parity bit stop bit parity bit stop bit mark state 1 frame 0 1d0d1d70/11 11 0d0d1 d70/1 serial data tdre tend lsi operation txi interrupt request generated tdre flag cleared to 0 user processing data written to tdr txi interrupt request generated tei interrupt request generated figure 14.5 example sci3 operation in transmission in asynchronous mode (8-bit data, parity, one stop bit)
section 14 serial communication interface 3 (sci3) rev.5.00 nov. 02, 2005 page 208 of 418 rej09b0028-0500 no yes start transmission read tdre flag in ssr [1] write transmit data to tdr yes no no yes read tend flag in ssr [2] no yes [3] clear pdr to 0 and set pcr to 1 clear te bit in scr3 to 0 tdre = 1 all data transmitted? tend = 1 break output? [1] read ssr and check that the tdre flag is set to 1, then write transmit data to tdr. when data is written to tdr, the tdre flag is automaticaly cleared to 0. [2] to continue serial transmission, read 1 from the tdre flag to confirm that writing is possible, then write data to tdr. when data is written to tdr, the tdre flag is automaticaly cleared to 0. [3] to output a break in serial transmission, after setting pcr to 1 and pdr to 0, clear txd in pmr1 to 0, then clear the te bit in scr3 to 0. figure 14.6 sample serial transmission flowchart (asynchronous mode)
section 14 serial communication interface 3 (sci3) rev.5.00 nov. 02, 2005 page 209 of 418 rej09b0028-0500 14.4.4 serial data reception figure 14.7 shows an example of operation for reception in asynchronous mode. in serial reception, the sci operates as described below. 1. the sci3 monitors the communication line. if a start bit is detected, the sci3 performs internal synchronization, receives data in rsr, and checks the parity bit and stop bit. 2. if an overrun error occurs (when reception of the next data is completed while the rdrf flag is still set to 1), the oer bit in ssr is set to 1. if the rie bit in scr3 is set to 1 at this time, an eri interrupt request is generated. recei ve data is not transferred to rdr. 3. if a parity error is detected, the per bit in ss r is set to 1 and receive data is transferred to rdr. if the rie bit in scr3 is set to 1 at this time, an eri interrupt request is generated. 4. if a framing error is detected (when the stop bit is 0), the fer bit in ssr is set to 1 and receive data is transferred to rdr. if the rie bit in scr3 is set to 1 at this time, an eri interrupt request is generated. 5. if reception is completed succe ssfully, the rdrf bit in ssr is set to 1, and receive data is transferred to rdr. if the rie bit in scr3 is set to 1 at this time, an rxi interrupt request is generated. continuous reception is possible because the rxi inte rrupt routine r eads the receive data transferred to rdr before reception of the next receive data has been completed. 1 frame start bit start bit receive data receive data parity bit stop bit parity bit stop bit mark state (idle state) 1 frame 0 1d0d1d70/11 01 0d0d1 d70/1 serial data rdrf fer lsi operation user processing rdrf cleared to 0 rdr data read framing error processing rxi request 0 stop bit detected eri request in response to framing error figure 14.7 example sci3 operation in reception in asynchronous mode (8-bit data, parity, one stop bit)
section 14 serial communication interface 3 (sci3) rev.5.00 nov. 02, 2005 page 210 of 418 rej09b0028-0500 table 14.5 shows the states of th e ssr status flags and receive da ta handling when a receive error is detected. if a receive error is detected, the rdrf flag retains its state before receiving data. reception cannot be resumed while a receive error flag is set to 1. accordingly, clear the oer, fer, per, and rdrf bits to 0 before resuming reception. figure 14.8 shows a sample flowchart for serial data reception. table 14.5 ssr status flag s and receive data handling ssr status flag rdrf * oer fer per receive data receive error type 1 1 0 0 lost overrun error 0 0 1 0 transferred to rdr framing error 0 0 0 1 transferred to rdr parity error 1 1 1 0 lost overrun error + framing error 1 1 0 1 lost overrun error + parity error 0 0 1 1 transferred to rdr framing error + parity error 1 1 1 1 lost overrun error + framing error + parity error note: * the rdrf flag retains the stat e it had before data reception.
section 14 serial communication interface 3 (sci3) rev.5.00 nov. 02, 2005 page 211 of 418 rej09b0028-0500 yes no start reception [1] no yes read rdrf flag in ssr [2] [3] clear re bit in scr3 to 0 read oer, per, and fer flags in ssr error processing (continued on next page) [4] read receive data in rdr yes no oer+per+fer = 1 rdrf = 1 all data received? [1] read the oer, per, and fer flags in ssr to identify the error. if a receive error occurs, performs the appropriate error processing. [2] read ssr and check that rdrf = 1, then read the receive data in rdr. the rdrf flag is cleared automatically. [3] to continue serial reception, before the stop bit for the current frame is received, read the rdrf flag and read rdr. the rdrf flag is cleared automatically. [4] if a receive error occurs, read the oer, per, and fer flags in ssr to identify the error. after performing the appropriate error processing, ensure that the oer, per, and fer flags are all cleared to 0. reception cannot be resumed if any of these flags are set to 1. in the case of a framing error, a break can be detected by reading the value of the input port corresponding to the rxd pin. (a) figure 14.8 sample seri al data reception flowchar t (asynchronous mode) (1)
section 14 serial communication interface 3 (sci3) rev.5.00 nov. 02, 2005 page 212 of 418 rej09b0028-0500 (a) error processing parity error processing yes no clear oer, per, and fer flags in ssr to 0 no yes no yes framing error processing no yes overrun error processing oer = 1 fer = 1 break? per = 1 [4] figure 14.8 sample serial reception data flowchart (2)
section 14 serial communication interface 3 (sci3) rev.5.00 nov. 02, 2005 page 213 of 418 rej09b0028-0500 14.5 operation in clocked synchronous mode figure 14.9 shows the general format for clocked synchronous communication. in clocked synchronous mode, data is transmitted or received synchronous with clock pulses. a single character in the transmit data co nsists of the 8-bit data starti ng from the lsb. in clocked synchronous serial communication, data on the transmission line is output from one falling edge of the serial clock to the next. in clocked synchronous mode, the sc i3 receives data in synchronous with the rising edge of the serial clock. after 8-bit data is output, the transmission line holds the msb state. in clocked synchronous mode, no parity or multiprocessor bit is added. inside the sci3, the transmitter and receiver are independent units, enabling full-duplex communication through the use of a common cloc k. both the transmitter and th e receiver also have a double- buffered structure, so data can be read or written during transmission or reception, enabling continuous data transfer. don?t care don?t care one unit of transfer data (character or frame) 8-bit bit 0 serial data synchronization clock bit 1 bit 3 bit 4 bit 5 lsb msb bit 2 bit 6 bit 7 * * note: * high except in continuous transfer figure 14.9 data format in clocked synchronous communication 14.5.1 clock either an internal clock generated by the on-chip baud rate generator or an external synchronization clock input at the sck3 pin can be selected, according to the setting of the com bit in smr and cke0 and cke1 bits in scr3. when the sci3 is operated on an internal clock, the serial clock is output from the sck3 pin. eight serial clock pulses are output in the transfer of one character, and when no transfer is performed the clock is fixed high. 14.5.2 sci3 initialization before transmitting and receiving data, the sci3 sh ould be initialized as described in a sample flowchart in figure 14.4.
section 14 serial communication interface 3 (sci3) rev.5.00 nov. 02, 2005 page 214 of 418 rej09b0028-0500 14.5.3 serial data transmission figure 14.10 shows an example of sci3 operation for transmission in clocked synchronous mode. in serial transmission, the sci3 operates as described below. 1. the sci3 monitors the tdre flag in ssr, and if the flag is 0, the sci re cognizes that data has been written to tdr, and transf ers the data from tdr to tsr. 2. the sci3 sets the tdre flag to 1 and starts tr ansmission. if the tie bit in scr3 is set to 1 at this time, a transmit data empty interrupt (txi) is generated. 3. 8-bit data is sent from the txd pin synchronized with the output clock when output clock mode has been specified, and synchronized with the input clock when use of an external clock has been specified. serial data is transmitted sequentially from the lsb (bit 0), from the txd pin. 4. the sci checks the tdre flag at the timing for sending the msb (bit 7). 5. if the tdre flag is cleared to 0, data is tr ansferred from tdr to tsr, and serial transmission of the next frame is started. 6. if the tdre flag is set to 1, the tend flag in ssr is set to 1, and the tdre flag maintains the output state of the last bit. if the teie bit in scr3 is set to 1 at this time, a tei interrupt request is generated. 7. the sck3 pin is fixed high. figure 14.11 shows a sample flowchart for serial data transmission. even if the tdre flag is cleared to 0, transmission will not start while a r eceive error flag (oer, fer, or per) is set to 1. make sure that the receive error flags are cleared to 0 before st arting transmission.
section 14 serial communication interface 3 (sci3) rev.5.00 nov. 02, 2005 page 215 of 418 rej09b0028-0500 serial clock serial data bit 1 bit 0 bit 7 bit 0 1 frame 1 frame bit 1 bit 6 bit 7 tdre tend lsi operation user processing txi interrupt request generated data written to tdr tdre flag cleared to 0 txi interrupt request generated tei interrupt request generated figure 14.10 example of sci3 operation in transmission in clocked synchronous mode
section 14 serial communication interface 3 (sci3) rev.5.00 nov. 02, 2005 page 216 of 418 rej09b0028-0500 no yes start transmission read tdre flag in ssr [1] write transmit data to tdr no yes no yes read tend flag in ssr [2] clear te bit in scr3 to 0 tdre = 1 all data transmitted? tend = 1 [1] read ssr and check that the tdre flag is set to 1, then write transmit data to tdr. when data is written to tdr, the tdre flag is automatically cleared to 0 and clocks are output to start the data transmission. [2] to continue serial transmission, be sure to read 1 from the tdre flag to confirm that writing is possible, then write data to tdr. when data is written to tdr, the tdre flag is automatically cleared to 0. figure 14.11 sample serial transmission flowchart (clocked synchronous mode)
section 14 serial communication interface 3 (sci3) rev.5.00 nov. 02, 2005 page 217 of 418 rej09b0028-0500 14.5.4 serial data reception (clocked synchronous mode) figure 14.12 shows an example of sci3 operation for reception in clocked synchronous mode. in serial reception, the sci3 operates as described below. 1. the sci3 performs internal initialization synchronous with a synchronous clock input or output, starts receiving data. 2. the sci3 stores the received data in rsr. 3. if an overrun error occurs (when reception of the next data is completed while the rdrf flag in ssr is still set to 1), the oer bit in ssr is set to 1. if the rie bit in scr3 is set to 1 at this time, an eri interrupt request is generated, re ceive data is not transferred to rdr, and the rdrf flag remains to be set to 1. 4. if reception is completed succe ssfully, the rdrf bit in ssr is set to 1, and receive data is transferred to rdr. if the rie bit in scr3 is set to 1 at this time, an rxi interrupt request is generated. serial clock serial data 1 frame 1 frame bit 0 bit 7 bit 7 bit 0 bit 1 bit 6 bit 7 rdrf oer lsi operation user processing rxi interrupt request generated rdr data read rdrf flag cleared to 0 rxi interrupt request generated eri interrupt request generated by overrun error overrun error processing rdr data has not been read (rdrf = 1) figure 14.12 example of sci3 reception operation in clocked synchronous mode reception cannot be resumed while a receive error fl ag is set to 1. accordingly, clear the oer, fer, per, and rdrf bits to 0 before resuming reception. figure 14.13 shows a sample flowchart for serial data reception.
section 14 serial communication interface 3 (sci3) rev.5.00 nov. 02, 2005 page 218 of 418 rej09b0028-0500 yes no start reception [1] [4] no yes read rdrf flag in ssr [2] [3] clear re bit in scr3 to 0 error processing (continued below) read receive data in rdr yes no oer = 1 rdrf = 1 all data received? read oer flag in ssr error processing overrun error processing clear oer flag in ssr to 0 [4] [1] read the oer flag in ssr to determine if there is an error. if an overrun error has occurred, execute overrun error processing. [2] read ssr and check that the rdrf flag is set to 1, then read the receive data in rdr. when data is read from rdr, the rdrf flag is automatically cleared to 0. [3] to continue serial reception, before the msb (bit 7) of the current frame is received, reading the rdrf flag and reading rdr should be finished. when data is read from rdr, the rdrf flag is automatically cleared to 0. [4] if an overrun error occurs, read the oer flag in ssr, and after performing the appropriate error processing, clear the oer flag to 0. reception cannot be resumed if the oer flag is set to 1. figure 14.13 sample serial reception flowchart (clocked synchronous mode)
section 14 serial communication interface 3 (sci3) rev.5.00 nov. 02, 2005 page 219 of 418 rej09b0028-0500 14.5.5 simultaneous serial data transmission and reception figure 14.14 shows a samp le flowchart for simulta neous serial transmit and receive operations. the following procedure should be used for simultaneous serial data transmit and receive operations. to switch from transmit mode to simultaneous transmit and receive mode, after checking that the sci3 has finished transmission and the tdre and tend flags are set to 1, clear te to 0. then simultaneously set te and re to 1 with a single instruction. to switch from receive mode to simultaneous transmit and receive mode , after checking that the sci3 has finished reception, clear re to 0. then after checking th at the rdrf and receive error flags (oer, fer, and per) are cleared to 0, simultaneously se t te and re to 1 with a single instruction.
section 14 serial communication interface 3 (sci3) rev.5.00 nov. 02, 2005 page 220 of 418 rej09b0028-0500 yes no start transmission/reception [3] error processing [4] read receive data in rdr yes no oer = 1 all data received? [1] read tdre flag in ssr no yes tdre = 1 write transmit data to tdr no yes rdrf = 1 read oer flag in ssr [2] read rdrf flag in ssr clear te and re bits in scr to 0 [1] read ssr and check that the tdre flag is set to 1, then write transmit data to tdr. when data is written to tdr, the tdre flag is automatically cleared to 0. [2] read ssr and check that the rdrf flag is set to 1, then read the receive data in rdr. when data is read from rdr, the rdrf flag is automatically cleared to 0. [3] to continue serial transmission/ reception, before the msb (bit 7) of the current frame is received, finish reading the rdrf flag, reading rdr. also, before the msb (bit 7) of the current frame is transmitted, read 1 from the tdre flag to confirm that writing is possible. then write data to tdr. when data is written to tdr, the tdre flag is automatically cleared to 0. when data is read from rdr, the rdrf flag is automatically cleared to 0. [4] if an overrun error occurs, read the oer flag in ssr, and after performing the appropriate error processing, clear the oer flag to 0. transmission/reception cannot be resumed if the oer flag is set to 1. for overrun error processing, see figure 14.13. figure 14.14 sample flowchart of simultaneo us serial transmit and receive operations (clocked synchronous mode)
section 14 serial communication interface 3 (sci3) rev.5.00 nov. 02, 2005 page 221 of 418 rej09b0028-0500 14.6 multiprocessor communication function use of the multiprocessor communi cation function enables data tr ansfer between a number of processors sharing communication lines by as ynchronous serial communication using the multiprocessor format, in which a multiprocessor bit is added to the transfer data. when multiprocessor co mmunication is performed, each receiving station is addressed by a unique id code. the serial communication cy cle consists of two component cy cles; an id transmission cycle that specifies the receiving station, and a data transmission cycl e. the multiprocessor bit is used to differentiate between the id transmission cy cle and the data transmission cycle. if the multiprocessor bit is 1, the cycle is an id transmi ssion cycle; if the multiprocessor bit is 0, the cycle is a data transmission cycle. figure 14.15 shows an example of inter-processor communication using the multiprocessor format. the transmitting station first sends the id code of the receiving station with wh ich it wants to perform serial co mmunication as data with a 1 multiprocessor bit added. it then sends transmit data as data with a 0 multiprocessor bit added. when data with a 1 multiprocessor bi t is received, the receiving statio n compares that data with its own id. the station whose id matc hes then receives the data sent next. stations whose ids do not match continue to skip data until data w ith a 1 multiprocessor b it is again received. the sci3 uses the mpie bit in scr3 to implement this function. when the mpie bit is set to 1, transfer of receive data from rsr to rdr, error flag detection, and setting the ssr status flags, rdrf, fer, and oer to 1, are inhibited until da ta with a 1 multiprocesso r bit is received. on reception of a receive character w ith a 1 multiprocessor bit, the mpbr bit in ssr is set to 1 and the mpie bit is automatically cleared, thus normal reception is resumed. if the rie bit in scr3 is set to 1 at this time, an rxi interrupt is generated. when the multiprocessor format is selected, the parity bit setting is rendered invalid. all other bit settings are the same as those in normal asynchronous mode. the clock used for multiprocessor communication is the same as that in normal asynchronous mode.
section 14 serial communication interface 3 (sci3) rev.5.00 nov. 02, 2005 page 222 of 418 rej09b0028-0500 transmitting station receiving station a receiving station b receiving station c receiving station d (id = 01) (id = 02) (id = 03) (id = 04) serial transmission line serial data id transmission cycle = receiving station specification data transmission cycle = data transmission to receiving station specified by id (mpb = 1) (mpb = 0) h'01 h'aa [legend] mpb: multiprocessor bit figure 14.15 example of communica tion using multip rocessor format (transmission of data h'aa to receiving station a) 14.6.1 multiprocessor seri al data transmission figure 14.16 shows a sample flowchart for multip rocessor serial data transmission. for an id transmission cycle, set the mpbt bit in ssr to 1 before transmission. for a data transmission cycle, clear the mpbt b it in ssr to 0 before transmission. all other sci3 operations are the same as those in asynchronous mode.
section 14 serial communication interface 3 (sci3) rev.5.00 nov. 02, 2005 page 223 of 418 rej09b0028-0500 no yes start transmission read tdre flag in ssr [1] set mpbt bit in ssr yes no no yes read tend flag in ssr [2] no yes [3] clear pdr to 0 and set pcr to 1 clear te bit in scr3 to 0 tdre = 1 all data transmitted? tend = 1 break output? write transmit data to tdr [1] read ssr and check that the tdre flag is set to 1, set the mpbt bit in ssr to 0 or 1, then write transmit data to tdr. when data is written to tdr, the tdre flag is automatically cleared to 0. [2] to continue serial transmission, be sure to read 1 from the tdre flag to confirm that writing is possible, then write data to tdr. when data is written to tdr, the tdre flag is automatically cleared to 0. [3] to output a break in serial transmission, set the port pcr to 1, clear pdr to 0, then clear the te bit in scr3 to 0. figure 14.16 sample multiprocessor serial tr ansmission flowchart
section 14 serial communication interface 3 (sci3) rev.5.00 nov. 02, 2005 page 224 of 418 rej09b0028-0500 14.6.2 multiprocessor s erial data reception figure 14.17 shows a sample flowchart for multipro cessor serial data reception. if the mpie bit in scr3 is set to 1, data is skipped until data w ith a 1 multiprocesso r bit is received. on receiving data with a 1 multiprocesso r bit, the receive data is transferre d to rdr. an rxi interrupt request is generated at this time. all other sci3 operations are the same as in asynchronous mode. figure 14.18 shows an example of sci3 operatio n for multiprocessor format reception.
section 14 serial communication interface 3 (sci3) rev.5.00 nov. 02, 2005 page 225 of 418 rej09b0028-0500 yes no start reception no yes [4] clear re bit in scr3 to 0 error processing (continued on next page) [5] yes no fer+oer = 1 rdrf = 1 all data received? set mpie bit in scr3 to 1 [1] [2] read oer and fer flags in ssr read rdrf flag in ssr [3] read receive data in rdr no yes [a] this station?s id? read oer and fer flags in ssr yes no read rdrf flag in ssr no yes fer+oer = 1 read receive data in rdr rdrf = 1 [1] set the mpie bit in scr3 to 1. [2] read oer and fer in ssr to check for errors. receive error processing is performed in cases where a receive error occurs. [3] read ssr and check that the rdrf flag is set to 1, then read the receive data in rdr and compare it with this station?s id. if the data is not this station?s id, set the mpie bit to 1 again. when data is read from rdr, the rdrf flag is automatically cleared to 0. [4] read ssr and check that the rdrf flag is set to 1, then read the data in rdr. [5] if a receive error occurs, read the oer and fer flags in ssr to identify the error. after performing the appropriate error processing, ensure that the oer and fer flags are all cleared to 0. reception cannot be resumed if either of these flags is set to 1. in the case of a framing error, a break can be detected by reading the rxd pin value. figure 14.17 sample multiprocessor serial reception flowchart (1)
section 14 serial communication interface 3 (sci3) rev.5.00 nov. 02, 2005 page 226 of 418 rej09b0028-0500 error processing yes no clear oer, and fer flags in ssr to 0 no yes no yes framing error processing overrun error processing oer = 1 fer = 1 break? [5] [a] figure 14.17 sample multiprocessor serial reception flowchart (2)
section 14 serial communication interface 3 (sci3) rev.5.00 nov. 02, 2005 page 227 of 418 rej09b0028-0500 1 frame start bit start bit receive data (id1) receive data (data1) mpb mpb stop bit stop bit mark state (idle state) 1 frame 0 1d0d1d711 11 0d0d1 d7 id1 0 serial data mpie rdrf rdr value rdr value lsi operation rxi interrupt request mpie cleared to 0 user processing rdrf flag cleared to 0 rxi interrupt request is not generated, and rdr retains its state rdr data read when data is not this station's id, mpie is set to 1 again 1 frame start bit start bit receive data (id2) receive data (data2) mpb mpb stop bit stop bit mark state (idle state) 1 frame 0 1d0d1d711 11 0 (a) when data does not match this receiver's id (b) when data matches this receiver's id d0 d1 d7 id2 data2 id1 0 serial data mpie rdrf lsi operation rxi interrupt request mpie cleared to 0 user processing rdrf flag cleared to 0 rxi interrupt request rdrf flag cleared to 0 rdr data read when data is this station's id, reception is continued rdr data read mpie set to 1 again figure 14.18 example of sc i3 operation in reception using multipro cessor format (example with 8-bit data, multiprocessor bit, one stop bit)
section 14 serial communication interface 3 (sci3) rev.5.00 nov. 02, 2005 page 228 of 418 rej09b0028-0500 14.7 interrupts the sci3 creates the following si x interrupt requests: transmission end, transmit data empty, receive data full, and receive erro rs (overrun error, framing error, and parity error). table 14.6 shows the interrupt sources. table 14.6 sci3 interrupt requests interrupt requests abbreviation interrupt sources receive data full rxi setting rdrf in ssr transmit data empty txi setting tdre in ssr transmission end tei setting tend in ssr receive error eri setting oer, fer, and per in ssr the initial value of the tdre flag in ssr is 1. thus, when the tie bit in scr3 is set to 1 before transferring the transmit data to td r, a txi interrupt request is gene rated even if the transmit data is not ready. the initial value of the tend flag in ssr is 1. thus, when the teie bit in scr3 is set to 1 before transferring the transmit data to tdr, a tei interrupt request is generated even if the transmit data has not been sent. it is possib le to make use of the most of these interrupt requests efficiently by transferring the transmit data to tdr in the interrupt routine. to prevent the generation of these interrupt requests (txi and te i), set the enable bits (tie and teie) that correspond to these in terrupt requests to 1, after transf erring the transmit data to tdr.
section 14 serial communication interface 3 (sci3) rev.5.00 nov. 02, 2005 page 229 of 418 rej09b0028-0500 14.8 usage notes 14.8.1 break detection and processing when framing error detection is performed, a break can be detected by reading the rxd pin value directly. in a break, the input from the rxd pin becomes all 0, setting the fer flag, and possibly the per flag. note that as the sci3 continues the receive operation after receiving a break, even if the fer flag is cleared to 0, it will be set to 1 again. 14.8.2 mark state and break sending when te is 0, the txd pin is used as an i/o port whose direction (input or output) and level are determined by pcr and pdr. this can be used to set the txd pin to mark state (high level) or send a break during serial data transmission. to maintain the communication line at mark state until te is set to 1, set both pcr and pdr to 1. as te is cleared to 0 at this point, the txd pin becomes an i/o port, and 1 is output from the txd pin. to send a break during serial transmission, first set pcr to 1 and pdr to 0, and then clear te to 0. when te is cleared to 0, the transmitter is initialized regardless of the current transmission st ate, the txd pin becomes an i/o port, and 0 is output from the txd pin. 14.8.3 receive error flags and transmit op erations (clocked synchronous mode only) transmission cannot be started when a receive error flag (oer, per, or fer) is set to 1, even if the tdre flag is cleared to 0. be sure to cl ear the receive error flag s to 0 before starting transmission. note also that receive error flags cannot be cleared to 0 even if the re bit is cleared to 0.
section 14 serial communication interface 3 (sci3) rev.5.00 nov. 02, 2005 page 230 of 418 rej09b0028-0500 14.8.4 receive data sampling timing and recept ion margin in asynchronous mode in asynchronous mode, the sci3 operates on a basic clock with a frequency of 16 times the transfer rate. in reception, the sci3 samples the falling edge of the start bit using the basic clock, and performs internal synchronization. receive data is latched internally at the rising edge of the 8th pulse of the basic clock as shown in figure 14.19. thus, the reception margin in asynchronous mode is given by formula (1) below. m = (0.5 ? ) ? ? (l ? 0.5) f 100(%) ? ? ? ? ? ? 1 2n d ? 0.5 n ... formula (1) where n : ratio of bit rate to clock (n = 16) d : clock duty (d = 0.5 to 1.0) l : frame length (l = 9 to 12) f : absolute value of clock rate deviation assuming values of f (absolute value of clock rate deviation) = 0 and d (clock duty) = 0.5 in formula (1), the reception margin can be given by the formula. m = {0.5 ? 1/(2 16)} 100 [%] = 46.875% however, this is only the computed value, and a margin of 20% to 30% should be allowed for in system design. internal basic clock 16 clocks 8 clocks receive data (rxd) synchronization sampling timing start bit d0 d1 data sampling timing 15 0 7 15 0 0 7 figure 14.19 receive data sampling timing in asynchronous mode
section 15 i 2 c bus interface 2 (iic2) ifiic10a_000020020200 rev.5.00 nov. 02, 2005 page 231 of 418 rej09b0028-0500 section 15 i 2 c bus interface 2 (iic2) the i 2 c bus interface 2 conforms to and pr ovides a subset of the philips i 2 c bus (inter-ic bus) interface functions. the register co nfiguration that controls the i 2 c bus differs partly from the philips configuration, however. figure 15.1 shows a block diagram of the i 2 c bus interface 2. figure 15.2 shows an example of i/o pin connections to external circuits. 15.1 features ? selection of i 2 c format or clocked synchronous serial format ? continuous transmission/reception since the shift register, transmit data register, and receive data register are independent from each other, the continuous transmi ssion/reception can be performed. i 2 c bus format ? start and stop conditions generated automatically in master mode ? selection of acknowledge output levels when receiving ? automatic loading of acknowledge bit when transmitting ? bit synchronization/wait function in master mode, the state of scl is monitored per bit, and the timing is synchronized automatically. if transmission/reception is not yet possible, set the scl to low un til preparations are completed. ? six interrupt sources transmit data empty (including slave-address matc h), transmit end, receive data full (including slave-address match), arbitration lost, nack detection, and stop condition detection ? direct bus drive two pins, scl and sda pins, function as nmos open-drain outputs when the bus drive function is selected. clocked synchronous format ? four interrupt sources transmit-data-empty, transmit-end, receive-data-full, and overrun error
section 15 i 2 c bus interface 2 (iic2) rev.5.00 nov. 02, 2005 page 232 of 418 rej09b0028-0500 scl iccr1 transfer clock generation circuit address comparator interrupt generator interrupt request bus state decision circuit arbitration decision circuit noise canceler noise canceler output control output control transmission/ reception control circuit iccr2 icmr icsr icier icdrr icdrs icdrt i 2 c bus control register 1 i 2 c bus control register 2 i 2 c bus mode register i 2 c bus status register i 2 c bus interrupt enable register i 2 c bus transmit data register i 2 c bus receive data register i 2 c bus shift register slave address register [legend] iccr1 : iccr2 : icmr : icsr : icier : icdrt : icdrr : icdrs : sar : sar sda internal data bus figure 15.1 block diagram of i 2 c bus interface 2
section 15 i 2 c bus interface 2 (iic2) rev.5.00 nov. 02, 2005 page 233 of 418 rej09b0028-0500 vcc vcc scl in scl out scl sda in sda out sda scl (master) (slave 1) (slave 2) sda scl in scl out scl sda in sda out sda scl in scl out scl sda in sda out sda figure 15.2 external circu it connections of i/o pins 15.2 input/output pins table 15.1 summarizes the input/output pins used by the i 2 c bus interface 2. table 15.1 i 2 c bus interface pins name abbreviation i/o function serial clock scl i/o iic se rial clock input/output serial data sda i/o iic serial data input/output 15.3 register descriptions the i 2 c bus interface 2 has the following registers: ? i 2 c bus control register 1 (iccr1) ? i 2 c bus control register 2 (iccr2) ? i 2 c bus mode register (icmr) ? i 2 c bus interrupt enable register (icier) ? i 2 c bus status register (icsr) ? i 2 c bus slave address register (sar)
section 15 i 2 c bus interface 2 (iic2) rev.5.00 nov. 02, 2005 page 234 of 418 rej09b0028-0500 ? i 2 c bus transmit data register (icdrt) ? i 2 c bus receive data register (icdrr) ? i 2 c bus shift register (icdrs) 15.3.1 i 2 c bus control register 1 (iccr1) iccr1 enables or disables the i 2 c bus interface 2, controls transm ission or reception, and selects master or slave mode, transmission or reception , and transfer clock frequ ency in master mode. bit bit name initial value r/w description 7 ice 0 r/w i 2 c bus interface enable 0: this module is halted. (scl and sda pins are set to port function.) 1: this bit is enabled for transfer operations. (scl and sda pins are bus drive state.) 6 rcvd 0 r/w reception disable this bit enables or disables the next operation when trs is 0 and icdrr is read. 0: enables next reception 1: disables next reception 5 4 mst trs 0 0 r/w r/w master/slave select transmit/receive select in master mode with the i 2 c bus format, when arbitration is lost, mst and trs are both reset by hardware, causing a transition to slave receive mode. modification of the trs bit should be made between transfer frames. after data receive has been started in slave receive mode, when the first seven bits of the receive data agree with the slave address that is set to sar and the eighth bit is 1, trs is automatically set to 1. if an overrun error occurs in master mode with the clock synchronous serial format, mst is cleared to 0 and slave receive mode is entered. operating modes are described below according to mst and trs combination. when clocked synchronous serial format is selected and mst is 1, clock is output. 00: slave receive mode 01: slave transmit mode 10: master receive mode 11: master transmit mode
section 15 i 2 c bus interface 2 (iic2) rev.5.00 nov. 02, 2005 page 235 of 418 rej09b0028-0500 bit bit name initial value r/w description 3 2 1 0 cks3 cks2 cks1 cks0 0 0 0 0 r/w r/w r/w r/w transfer clock select 3 to 0 these bits should be set according to the necessary transfer rate (see table 15.2) in master mode. in slave mode, these bits are used for re servation of the setup time in transmit mode. the time is 10 t cyc when cks3 = 0 and 20 t cyc when cks3 = 1. table 15.2 transfer rate bit 3 bit 2 bit 1 bit 0 transfer rate cks3 cks2 cks1 cks0 clock = 5 mhz = 8 mhz = 10 mhz = 16 mhz = 20 mhz 0 /28 179 khz 286 khz 357 khz 571 khz 714 khz 0 1 /40 125 khz 200 khz 250 khz 400 khz 500 khz 0 /48 104 khz 167 khz 208 khz 333 khz 417 khz 0 1 1 /64 78.1 khz 125 khz 156 khz 250 khz 313 khz 0 /80 62.5 khz 100 khz 125 khz 200 khz 250 khz 0 1 /100 50.0 khz 80.0 khz 100 khz 160 khz 200 khz 0 /112 44.6 khz 71.4 khz 89.3 khz 143 khz 179 khz 0 1 1 1 /128 39.1 khz 62.5 khz 78.1 khz 125 khz 156 khz 0 /56 89.3 khz 143 khz 179 khz 286 khz 357 khz 0 1 /80 62.5 khz 100 khz 125 khz 200 khz 250 khz 0 /96 52.1 khz 83.3 khz 104 khz 167 khz 208 khz 0 1 1 /128 39.1 khz 62.5 khz 78.1 khz 125 khz 156 khz 0 /160 31.3 khz 50.0 khz 62.5 khz 100 khz 125 khz 0 1 /200 25.0 khz 40.0 khz 50.0 khz 80.0 khz 100 khz 0 /224 22.3 khz 35.7 khz 44.6 khz 71.4 khz 89.3 khz 1 1 1 1 /256 19.5 khz 31.3 khz 39.1 khz 62.5 khz 78.1 khz
section 15 i 2 c bus interface 2 (iic2) rev.5.00 nov. 02, 2005 page 236 of 418 rej09b0028-0500 15.3.2 i 2 c bus control register 2 (iccr2) iccr1 issues start/stop conditions, manipulates the sda pin, monitors the scl pin, and controls reset in the control part of the i 2 c bus interface 2. bit bit name initial value r/w description 7 bbsy 0 r/w bus busy this bit enables to confirm whether the i 2 c bus is occupied or released and to issue start/stop conditions in master mode. with the clocked synchronous serial format, this bit has no meaning. with the i 2 c bus format, this bit is set to 1 when the sda level changes from high to low under the condition of scl = high, assuming that the start condition has been issued. this bit is cleared to 0 when the sda level changes from low to high under the condition of scl = high, assu ming that the stop condition has been issued. write 1 to bbsy and 0 to scp to issue a start condition. follow this procedure when also re- transmitting a start condition. write 0 in bbsy and 0 in scp to issue a stop condition. to issue start/stop conditions, use the mov instruction. 6 scp 1 w start/stop issue condition disable the scp bit controls the iss ue of start/stop conditions in master mode. to issue a start condition, write 1 in bbsy and 0 in scp. a retransmit start condition is issued in the same way. to issue a stop condition, write 0 in bbsy and 0 in scp. this bit is always read as 1. if 1 is written, the data is not stored. 5 sdao 1 r/w sda output value control this bit is used with sdaop when modifying output level of sda. this bit should not be manipulated during transfer. 0: when reading, sda pin outputs low. when writing, sda pin is changed to output low. 1: when reading, sda pin outputs high. when writing, sda pin is changed to output hi-z (outputs high by external pull-up resistance).
section 15 i 2 c bus interface 2 (iic2) rev.5.00 nov. 02, 2005 page 237 of 418 rej09b0028-0500 bit bit name initial value r/w description 4 sdaop 1 r/w sdao write protect this bit controls change of output level of the sda pin by modifying the sdao bit. to change the output level, clear sdao and sdaop to 0 or set sdao to 1 and clear sdaop to 0 by the mov instruction. this bit is always read as 1. 3 sclo 1 r this bit monitors scl output level. when sclo is 1, scl pin outputs high. when sclo is 0, scl pin outputs low. 2 ? 1 ? reserved this bit is always read as 1, and cannot be modified. 1 iicrst 0 r/w iic control part reset this bit resets the control part except for i 2 c registers. if this bit is set to 1 when hang-up occurs because of communication failure during i 2 c operation, i 2 c control part can be reset without setting ports and initializing registers. 0 ? 1 ? reserved this bit is always read as 1, and cannot be modified. 15.3.3 i 2 c bus mode register (icmr) icmr selects whether the msb or lsb is transfer red first, performs master mode wait control, and selects the tran sfer bit count. bit bit name initial value r/w description 7 mls 0 r/w msb-first/lsb-first select 0: msb-first 1: lsb-first set this bit to 0 when the i 2 c bus format is used. 6 wait 0 r/w wait insertion bit in master mode with the i 2 c bus format, this bit selects whether to insert a wait after data transfer except the acknowledge bit. when wait is set to 1, after the fall of the clock for the final data bit, low period is extended for two transfer clocks. if wait is cleared to 0, data and acknowledge bits are transferred consecutively with no wait inserted. the setting of this bit is invalid in slave mode with the i 2 c bus format or with the clocked synchronous serial format.
section 15 i 2 c bus interface 2 (iic2) rev.5.00 nov. 02, 2005 page 238 of 418 rej09b0028-0500 bit bit name initial value r/w description 5, 4 ? all 1 ? reserved these bits are always read as 1, and cannot be modified. 3 bcwp 1 r/w bc write protect this bit controls the bc2 to bc0 modifications. when modifying bc2 to bc0, this bit should be cleared to 0 and use the mov instruction. in clock synchronous serial mode, bc should not be modified. 0: when writing, values of bc2 to bc0 are set. 1: when reading, 1 is always read. when writing, settings of bc2 to bc0 are invalid. 2 1 0 bc2 bc1 bc0 0 0 0 r/w r/w r/w bit counter 2 to 0 these bits specify the number of bits to be transferred next. when read, the remaining number of transfer bits is indicated. with the i 2 c bus format, the data is transferred with one addition acknowledge bit. bit bc2 to bc0 settings should be made during an interval between transfer frames. if bits bc2 to bc0 are set to a value other than 000, the setting should be made while the scl pin is low. the value returns to 000 at the end of a data transfer, including the acknowledge bit. with the clock synchronous serial format, these bits should not be modified. i 2 c bus format clock synchronous serial format 000: 9 bits 000: 8 bits 001: 2 bits 001: 1 bits 010: 3 bits 010: 2 bits 011: 4 bits 011: 3 bits 100: 5 bits 100: 4 bits 101: 6 bits 101: 5 bits 110: 7 bits 110: 6 bits 111: 8 bits 111: 7 bits
section 15 i 2 c bus interface 2 (iic2) rev.5.00 nov. 02, 2005 page 239 of 418 rej09b0028-0500 15.3.4 i 2 c bus interrupt enable register (icier) icier enables or disables interrupt sources and acknowledge bits, sets acknowledge bits to be transferred, and conf irms acknowledge bits to be received. bit bit name initial value r/w description 7 tie 0 r/w transmit interrupt enable when the tdre bit in icsr is set to 1, this bit enables or disables the transmit dat a empty interrupt (txi). 0: transmit data empty interru pt request (txi) is disabled. 1: transmit data empty interru pt request (txi) is enabled. 6 teie 0 r/w transmit end interrupt enable this bit enables or disables the transmit end interrupt (tei) at the rising of the nint h clock while the tdre bit in icsr is 1. tei can be canceled by clearing the tend bit or the teie bit to 0. 0: transmit end interrupt request (tei) is disabled. 1: transmit end interrupt request (tei) is enabled. 5 rie 0 r/w receive interrupt enable this bit enables or disables the receive data full interrupt request (rxi) and the overrun error interrupt request (eri) with the clocked synchronous format, when a receive data is transferred fr om icdrs to icdrr and the rdrf bit in icsr is set to 1. rxi can be canceled by clearing the rdrf or rie bit to 0. 0: receive data full interrupt request (rxi) and overrun error interrupt request (eri) with the clocked synchronous format are disabled. 1: receive data full interrupt request (rxi) and overrun error interrupt request (eri) with the clocked synchronous format are enabled. 4 nakie 0 r/w nack receive interrupt enable this bit enables or disables the nack receive interrupt request (naki) and the overrun error (setting of the ove bit in icsr) interrupt request (eri) with the clocked synchronous format, when the nackf and al bits in icsr are set to 1. naki can be canceled by clearing the nackf, ove, or nakie bit to 0. 0: nack receive interrupt request (naki) is disabled. 1: nack receive interrupt request (naki) is enabled.
section 15 i 2 c bus interface 2 (iic2) rev.5.00 nov. 02, 2005 page 240 of 418 rej09b0028-0500 bit bit name initial value r/w description 3 stie 0 r/w stop condition detection interrupt enable 0: stop condition detection interrupt request (stpi) is disabled. 1: stop condition detection interrupt request (stpi) is enabled. 2 acke 0 r/w acknowledge bit judgement select 0: the value of the receive acknowledge bit is ignored, and continuous transfer is performed. 1: if the receive acknowledge bit is 1, continuous transfer is halted. 1 ackbr 0 r receive acknowledge in transmit mode, this bit stores the acknowledge data that are returned by the receive device. this bit cannot be modified. 0: receive acknowledge = 0 1: receive acknowledge = 1 0 ackbt 0 r/w transmit acknowledge in receive mode, this bit specif ies the bit to be sent at the acknowledge timing. 0: 0 is sent at the acknowledge timing. 1: 1 is sent at the acknowledge timing.
section 15 i 2 c bus interface 2 (iic2) rev.5.00 nov. 02, 2005 page 241 of 418 rej09b0028-0500 15.3.5 i 2 c bus status register (icsr) icsr performs confirmation of interrupt request flags and status. bit bit name initial value r/w description 7 tdre 0 r/w transmit data register empty [setting conditions] ? when data is transferred from icdrt to icdrs and icdrt becomes empty ? when trs is set ? when a start condition (including re-transfer) has been issued ? when transmit mode is entered from receive mode in slave mode [clearing conditions] ? when 0 is written in tdre after reading tdre = 1 ? when data is written to icdrt with an instruction 6 tend 0 r/w transmit end [setting conditions] ? when the ninth clock of scl rises with the i 2 c bus format while the tdre flag is 1 ? when the final bit of transmit frame is sent with the clock synchronous serial format [clearing conditions] ? when 0 is written in tend after reading tend = 1 ? when data is written to icdrt with an instruction 5 rdrf 0 r/w receive data register full [setting condition] ? when a receive data is transferred from icdrs to icdrr [clearing conditions] ? when 0 is written in rdrf after reading rdrf = 1 ? when icdrr is read with an instruction
section 15 i 2 c bus interface 2 (iic2) rev.5.00 nov. 02, 2005 page 242 of 418 rej09b0028-0500 bit bit name initial value r/w description 4 nackf 0 r/w no acknowledge detection flag [setting condition] ? when no acknowledge is detected from the receive device in transmission while the acke bit in icier is 1 [clearing condition] ? when 0 is written in nackf after reading nackf = 1 3 stop 0 r/w stop condition detection flag [setting conditions] ? in master mode, when a stop condition is detected after frame transfer ? in slave mode, when a stop condition is detected after the general call address or the first byte slave address, next to detection of start condition, accords with the address set in sar [clearing condition] ? when 0 is written in stop after reading stop = 1
section 15 i 2 c bus interface 2 (iic2) rev.5.00 nov. 02, 2005 page 243 of 418 rej09b0028-0500 bit bit name initial value r/w description 2 al/ove 0 r/w arbitration lost flag/overrun error flag this flag indicates that arbitr ation was lost in master mode with the i 2 c bus format and that the final bit has been received while rdrf = 1 with the clocked synchronous format. when two or more master devices attempt to seize the bus at nearly the same time, if the i 2 c bus interface detects data differing from the data it sent, it sets al to 1 to indicate that the bus has been taken by another master. [setting conditions] ? if the internal sda and sda pin disagree at the rise of scl in master transmit mode ? when the sda pin outputs high in master mode while a start condition is detected ? when the final bit is received with the clocked synchronous format while rdrf = 1 [clearing condition] ? when 0 is written in al/ove after reading al/ove = 1 1 aas 0 r/w slave addr ess recognition flag in slave receive mode, this flag is set to 1 if the first frame following a start condition matches bits sva6 to sva0 in sar. [setting conditions] ? when the slave address is detected in slave receive mode ? when the general call address is detected in slave receive mode. [clearing condition] ? when 0 is written in aas after reading aas = 1 0 adz 0 r/w general call address recognition flag this bit is valid in i 2 c bus format slave receive mode. [setting condition] ? when the general call address is detected in slave receive mode [clearing condition] ? when 0 is written in adz after reading adz = 1
section 15 i 2 c bus interface 2 (iic2) rev.5.00 nov. 02, 2005 page 244 of 418 rej09b0028-0500 15.3.6 slave address register (sar) sar selects the communica tion format and sets the slave address. when the chip is in slave mode with the i 2 c bus format, if the upper 7 bits of sar match the upper 7 bits of the first frame received after a start condition, the ch ip operates as the slave device. bit bit name initial value r/w description 7 to 1 sva6 to sva0 all 0 r/w slave address 6 to 0 these bits set a unique address in bits sva6 to sva0, differing form the addresses of other slave devices connected to the i 2 c bus. 0 fs 0 r/w format select 0: i 2 c bus format is selected. 1: clocked synchronous seri al format is selected.
section 15 i 2 c bus interface 2 (iic2) rev.5.00 nov. 02, 2005 page 245 of 418 rej09b0028-0500 15.3.7 i 2 c bus transmit data register (icdrt) icdrt is an 8-bit readable/writable register that stores the transmit data. when icdrt detects the space in the shift register (icdrs), it transfers th e transmit data which is written in icdrt to icdrs and starts transferring data. if the next transfer data is written to icdrt during transferring data of icdrs, conti nuous transfer is possible. if the mls bit of icmr is set to 1 and when the data is written to icdrt, the msb/lsb inverted data is read. the initial value of icdrt is h?ff. the initial value of icdrt is h?ff. 15.3.8 i 2 c bus receive data register (icdrr) icdrr is an 8-bit register that stores the receiv e data. when data of one byte is received, icdrr transfers the receive data from icdrs to icdrr and the next data can be received. icdrr is a receive-only register, therefore the cpu cannot write to this regist er. the initial value of icdrr is h?ff. 15.3.9 i 2 c bus shift register (icdrs) icdrs is a register that is used to transfer/receive data. in transm ission, data is transferred from icdrt to icdrs and the data is sent from the sda pin. in reception, data is transferred from icdrs to icdrr after data of one byte is received. this register cannot be read directly from the cpu.
section 15 i 2 c bus interface 2 (iic2) rev.5.00 nov. 02, 2005 page 246 of 418 rej09b0028-0500 15.4 operation the i 2 c bus interface can communicate either in i 2 c bus mode or clocked synchronous serial mode by setting fs in sar. 15.4.1 i 2 c bus format figure 15.3 shows the i 2 c bus formats. figure 15.4 shows the i 2 c bus timing. the first frame following a start condition always consists of 8 bits. s sla r/ w a data a a/ a p 111 1 n 7 1 m (a) i 2 c bus format (fs = 0) (b) i 2 c bus format (start condition retransmission, fs = 0) n: transfer bit count (n = 1 to 8) m: transfer frame count (m 1) s sla r/ w a data 11 1 n1 7 1 m1 s sla r/ w a data a/ a p 11 1 n2 7 1 m2 1 1 1 a/ a n1 and n2: transfer bit count (n1 and n2 = 1 to 8) m1 and m2: transfer frame count (m1 and m2 1) 11 figure 15.3 i 2 c bus formats sda scl s 1-7 sla 8 r/ w 9 a 1-7 data 89 1-7 89 a data p a figure 15.4 i 2 c bus timing legend s: start condition. the master device drives sda from high to low while scl is high. sla: slave address
section 15 i 2 c bus interface 2 (iic2) rev.5.00 nov. 02, 2005 page 247 of 418 rej09b0028-0500 r/ w : indicates the direction of da ta transfer: from the slave devi ce to the master device when r/ w is 1, or from the master device to the slave device when r/ w is 0. a: acknowledge. the receive device drives sda to low. data: transfer data p: stop condition. the master device drives sda from low to high while scl is high. 15.4.2 master transmit operation in master transmit mode, the master device outputs the transmit clock and transmit data, and the slave device returns an acknowledge signal. for ma ster transmit mode operation timing, refer to figures 15.5 and 15.6. the transmission procedure and operations in master transmit mode are described below. 1. set the ice bit in iccr1 to 1. set the mls and wait bits in icmr and the cks3 to cks0 bits in iccr1 to 1. (initial setting) 2. read the bbsy flag in iccr2 to confirm that the bus is free. set the mst and trs bits in iccr1 to select master transmit mode. then , write 1 to bbsy and 0 to scp using mov instruction. (start condition issued) this generates the start condition. 3. after confirming that tdre in icsr has been set, write the transmit data (the first byte data show the slave address and r/ w ) to icdrt. at this time, tdre is automatically cleared to 0, and data is transferred from icdr t to icdrs. tdre is set again. 4. when transmission of one byte data is completed while tdre is 1, tend in icsr is set to 1 at the rise of the 9th transmit clock pulse. read the ackbr bit in icier, and confirm that the slave device has been selected. then, write second byte data to icdrt. when ackbr is 1, the slave device has not been acknowledged, so issue the stop condition. to issue the stop condition, write 0 to bbsy and scp using mov instruction. scl is fixed low until the transmit data is prepared or the stop condition is issued. 5. the transmit data after the second byte is written to icdrt every time tdre is set. 6. write the number of bytes to be transmitted to icdrt. wait until tend is set (the end of last byte data transmission) while tdre is 1, or wait for nack (nackf in icsr = 1) from the receive device while acke in icier is 1. then , issue the stop condition to clear tend or nackf. 7. when the stop bit in icsr is set to 1, the operation returns to the slave receive mode.
section 15 i 2 c bus interface 2 (iic2) rev.5.00 nov. 02, 2005 page 248 of 418 rej09b0028-0500 tdre scl (master output) sda (master output) sda (slave output) tend [5] write data to icdrt (third byte) icdrt icdrs [2] instruction of start condition issuance [3] write data to icdrt (first byte) [4] write data to icdrt (second byte) user processing 1 bit 7 slave address address + r/ w data 1 data 1 data 2 address + r/ w bit 6 bit 7 bit 6 bit 5bit 4bit 3bit 2bit 1bit 0 212 3456789 a r/ w figure 15.5 master transmit mode operation timing (1) tdre [6] issue stop condition. clear tend. [7] set slave receive mode tend icdrt icdrs 1 9 23456789 a a/ a scl (master output) sda (master output) sda (slave output) bit 7 bit 6 data n data n bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 [5] write data to icdrt user processing figure 15.6 master transmit mode operation timing (2)
section 15 i 2 c bus interface 2 (iic2) rev.5.00 nov. 02, 2005 page 249 of 418 rej09b0028-0500 15.4.3 master receive operation in master receive mode, the master device outputs th e receive clock, receives data from the slave device, and returns an acknowledge signal. for master receive mode operation timing, refer to figures 15.7 and 15.8. the reception procedure and operations in master receive mode are shown below. 1. clear the tend bit in icsr to 0, then clear the trs bit in iccr1 to 0 to switch from master transmit mode to master receive mode . then, clear the tdre bit to 0. 2. when icdrr is read (dummy data read), reception is started, and the receive clock is output, and data received, in synchronization with the internal clock. the master device outputs the level specified by ackbt in icier to sda, at the 9th receive clock pulse. 3. after the reception of first frame data is complete d, the rdrf bit in icst is set to 1 at the rise of 9th receive clock pulse. at this time, the r eceive data is read by reading icdrr, and rdrf is cleared to 0. 4. the continuous reception is performed by reading icdrr every time rdrf is set. if 8th receive clock pulse falls after reading icdrr by the other processing while rdrf is 1, scl is fixed low until icdrr is read. 5. if next frame is the last receive data, set th e rcvd bit in iccr1 to 1 before reading icdrr. this enables the issuance of the stop condition after the next reception. 6. when the rdrf bit is set to 1 at rise of th e 9th receive clock pulse, issue the stage condition. 7. when the stop bit in icsr is set to 1, read icdrr. then clear the rcvd bit to 0. 8. the operation returns to the slave receive mode.
section 15 i 2 c bus interface 2 (iic2) rev.5.00 nov. 02, 2005 page 250 of 418 rej09b0028-0500 tdre tend icdrs icdrr [1] clear tdre after clearing tend and trs [2] read icdrr (dummy read) [3] read icdrr 1 a 21 3456789 9 a trs rdrf scl (master output) sda (master output) sda (slave output) bit 7 master transmit mode master receive mode bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 user processing data 1 data 1 figure 15.7 master receive mode operation timing (1)
section 15 i 2 c bus interface 2 (iic2) rev.5.00 nov. 02, 2005 page 251 of 418 rej09b0028-0500 rdrf rcvd icdrs icdrr data n-1 data n data n data n-1 [5] read icdrr after setting rcvd [6] issue stop condition [7] read icdrr, and clear rcvd [8] set slave receive mode 1 9 23456789 a a/ a scl (master output) sda (master output) sda (slave output) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 user processing figure 15.8 master receive mode operation timing (2) 15.4.4 slave transmit operation in slave transmit mode, the slave device outputs th e transmit data, while the master device outputs the receive clock and returns an acknowledge sign al. for slave transmit mode operation timing, refer to figures 15.9 and 15.10. the transmission procedure and operations in slave transmit mode are described below. 1. set the ice bit in iccr1 to 1. set the mls and wait bits in icmr and the cks3 to cks0 bits in iccr1 to 1. (initial setting) set the mst and trs bits in iccr1 to select slave receive mode, and wait until the slave address matches. 2. when the slave address matches in the first frame following detection of the start condition, the slave device outputs the leve l specified by ackbt in icier to sda, at the rise of the 9th clock pulse. at this time, if the 8th bit data (r/ w ) is 1, the trs and icsr bits in iccr1 are set to 1, and the mode changes to slave transmit mode automatically. the continuous transmission is performed by writing transmit data to icdrt every time tdre is set. 3. if tdre is set after writing last transmit data to icdrt, wait until tend in icsr is set to 1, with tdre = 1. when te nd is set, clear tend. 4. clear trs for the end processing, and read icdrr (dummy read). scl is free. 5. clear tdre.
section 15 i 2 c bus interface 2 (iic2) rev.5.00 nov. 02, 2005 page 252 of 418 rej09b0028-0500 tdre tend icdrs icdrr 1 a 21 3456789 9 a trs icdrt scl (master output) slave receive mode slave transmit mode sda (master output) sda (slave output) scl (slave output) bit 7 bit 7 data 1 data 1 data 2 data 3 data 2 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 [2] write data to icdrt (data 1) [2] write data to icdrt (data 2) [2] write data to icdrt (data 3) user processing figure 15.9 slave transmit mode operation timing (1)
section 15 i 2 c bus interface 2 (iic2) rev.5.00 nov. 02, 2005 page 253 of 418 rej09b0028-0500 tdre data n tend icdrs icdrr 1 9 23456789 a trs icdrt a scl (master output) sda (master output) sda (slave output) scl (slave output) bit 7 slave transmit mode slave receive mode bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 [3] clear tend [5] clear tdre [4] read icdrr (dummy read) after clearing trs user processing figure 15.10 slave transmit mode operation timing (2) 15.4.5 slave receive operation in slave receive mode, the master device outputs the transmit clock and transmit data, and the slave device returns an acknowledge signal. fo r slave receive mode ope ration timing, refer to figures 15.11 and 15.12. the reception procedure and operations in slave receive mode are described below. 1. set the ice bit in iccr1 to 1. set the mls and wait bits in icmr and the cks3 to cks0 bits in iccr1 to 1. (initial setting) set the mst and trs bits in iccr1 to select slave receive mode, and wait until the slave address matches. 2. when the slave address matches in the first frame following detection of the start condition, the slave device outputs the leve l specified by ackbt in icier to sda, at the rise of the 9th clock pulse. at the same time, rdrf in icsr is set to read icdrr (d ummy read). (since the read data show the slave address and r/ w , it is not used.)
section 15 i 2 c bus interface 2 (iic2) rev.5.00 nov. 02, 2005 page 254 of 418 rej09b0028-0500 3. read icdrr every time rdrf is set. if 8th r eceive clock pulse falls while rdrf is 1, scl is fixed low until icdrr is read. the change of the acknowledge before reading icdrr, to be returned to the master device, is reflected to the next transmit frame. 4. the last byte data is read by reading icdrr. icdrs icdrr 12 1 345678 9 9 a a rdrf data 1 data 2 data 1 scl (master output) sda (master output) sda (slave output) scl (slave output) bit 7 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 [2] read icdrr (dummy read) [2] read icdrr user processing figure 15.11 slave receive mode operation timing (1) icdrs icdrr 12345678 9 9 a a rdrf scl (master output) sda (master output) sda (slave output) scl (slave output) user processing bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 data 1 [3] set ackbt [3] read icdrr [4] read icdrr data 2 data 1 figure 15.12 slave receive mode operation timing (2)
section 15 i 2 c bus interface 2 (iic2) rev.5.00 nov. 02, 2005 page 255 of 418 rej09b0028-0500 15.4.6 clocked synchronous serial format this module can be operated with the clocked synchronous serial format, by setting the fs bit in sar to 1. when the mst bit in iccr1 is 1, the transfer clock output from scl is selected. when mst is 0, the external clock input is selected. data transfer format figure 15.13 shows the clocked synchronous serial transfer format. the transfer data is output from the rise to the fa ll of the scl clock, and the data at the rising edge of the scl clock is guaranteed. the mls bit in icmr sets the order of data transfer, in either the msb first or lsb first. the output level of sda can be changed during the transfer wait, by the sdao bit in iccr2. sda bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 scl figure 15.13 clocked synchronous serial transfer format transmit operation in transmit mode, transmit data is output from sda, in synchronization with the fall of the transfer clock. the transfer clock is output when mst in iccr1 is 1, and is input when mst is 0. for transmit mode operation timing, refer to figure 15.14. the transmission procedure and operations in transmit mode are described below. 1. set the ice bit in iccr1 to 1. set the mst and cks3 to cks0 bits in iccr1 to 1. (initial setting) 2. set the trs bit in iccr1 to select the transmit mode. then, tdre in icsr is set. 3. confirm that tdre has been set. then, write the transmit data to icdrt. the data is transferred from icdrt to icdrs, and td re is set automatically. the continuous transmission is performed by writing data to icdrt every time tdre is set. when changing from transmit mode to receive mode, clear trs while tdre is 1.
section 15 i 2 c bus interface 2 (iic2) rev.5.00 nov. 02, 2005 page 256 of 418 rej09b0028-0500 12 781 78 1 scl trs bit 0 data 1 data 1 data 2 data 3 data 2 data 3 bit 6 bit 7 bit 0 bit 6 bit 7 bit 0 bit 1 sda (output) tdre icdrt icdrs user processing [3] write data to icdrt [3] write data to icdrt [3] write data to icdrt [3] write data to icdrt [2] set trs figure 15.14 transmit mode operation timing receive operation in receive mode, data is latched at the rise of the transfer clock. the transfer clock is output when mst in iccr1 is 1, and is input when mst is 0. for receive mode operation timing, refer to figure 15.15. the reception pro cedure and operations in receiv e mode are described below. 1. set the ice bit in iccr1 to 1. set the mst and cks3 to cks0 bits in iccr1 to 1. (initial setting) 2. when the transfer clock is output, set mst to 1 to start outputting the receive clock. 3. when the receive operation is completed, da ta is transferred from icdrs to icdrr and rdrf in icsr is set. when mst = 1, the ne xt byte can be received, so the clock is continually output. the continuous reception is performed by reading icdrr every time rdrf is set. when the 8th clock is risen while rdrf is 1, the overrun is detected and al/ove in icsr is set. at this time, the pr evious reception data is retained in icdrr. 4. to stop receiving when mst = 1, set rcvd in iccr1 to 1, then read icdrr. then, scl is fixed high after receiving the next byte data.
section 15 i 2 c bus interface 2 (iic2) rev.5.00 nov. 02, 2005 page 257 of 418 rej09b0028-0500 12 781 7812 scl mst trs rdrf icdrs icdrr sda (input) bit 0 bit 6 bit 7 bit 0 bit 6 bit 7 bit 0 bit 1 user processing data 1 data 1 data 2 data 2 data 3 [2] set mst (when outputting the clock) [3] read icdrr [3] read icdrr figure 15.15 receive mode operation timing 15.4.7 noise canceler the logic levels at the scl and sda pins are routed through noise cancelers before being latched internally. figure 15.16 shows a block diagram of the noise canceler circuit. the noise canceler consists of two cascaded la tches and a match detector. the scl (or sda) input signal is sampled on the system clock, but is not passed forward to the next circuit unless the outputs of both latches agree. if they do not agree, the previous value is held. c q d march detector internal scl or sda signal scl or sda input signal sampling clock sampling clock system clock period latch latch c q d figure 15.16 block di agram of noise conceler
section 15 i 2 c bus interface 2 (iic2) rev.5.00 nov. 02, 2005 page 258 of 418 rej09b0028-0500 15.4.8 example of use flowcharts in respective modes that use the i 2 c bus interface are shown in figures 15.17 to 15.20. bbsy=0 ? no tend=1 ? no yes start [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [13] [14] [15] initialize set mst and trs in iccr1 to 1. write 1 to bbsy and 0 to scp. write transmit data in icdrt write 0 to bbsy and scp set mst to 1 and trs to 0 in iccr1 read bbsy in iccr2 read tend in icsr read ackbr in icier mater receive mode yes ackbr=0 ? write transmit data in icdrt read tdre in icsr read tend in icsr clear tend in icsr read stop in icsr clear tdre in icsr end write transmit data in icdrt transmit mode? no yes tdre=1 ? last byte? stop=1 ? no no no no no yes yes tend=1 ? yes yes yes [1] test the status of the scl and sda lines. [2] set master transmit mode. [3] issue the start condition. [4] set the first byte (slave address + r/ w ) of transmit data. [5] wait for 1 byte to be transmitted. [6] test the acknowledge transferred from the specified slave device. [7] set the second and subsequent bytes (except for the final byte) of transmit data. [8] wait for icdrt empty. [9] set the last byte of transmit data. [10] wait for last byte to be transmitted. [11] clear the tend flag. [12] clear stop flag. [13] issue the stop condition. [14] wait for the creation of stop condition. [15] set slave receive mode. clear tdre. [12] clear stop in iscr figure 15.17 sample flowch art for master transmit mode
section 15 i 2 c bus interface 2 (iic2) rev.5.00 nov. 02, 2005 page 259 of 418 rej09b0028-0500 no yes rdrf=1 ? no yes rdrf=1 ? last receive - 1? mater receive mode clear tend in icsr clear trs in iccr1 to 0 clear tdre in icsr clear ackbt in icier to 0 dummy-read icdrr read rdrf in icsr read icdrr set ackbt in icier to 1 set rcvd in iccr1 to 1 read icdrr read rdrf in icsr write 0 to bbsy and scp read stop in icsr read icdrr clear rcvd in iccr1 to 0 clear mst in iccr1 to 0 end note: do not activate an interrupt during the execution of steps [1] to [3]. no yes stop=1 ? no yes [1] clear tend, select master receive mode, and then clear tdre. * [2] set acknowledge to the transmit device. * [3] dummy-read icddr. * [4] wait for 1 byte to be received [5] check whether it is the (last receive - 1). [6] read the receive data last. [7] set acknowledge of the final byte. disable continuous reception (rcvd = 1). [8] read the (final byte - 1) of receive data. [9] wait for the last byte to be receive. [10] clear stop flag. [11] issue the stop condition. [12] wait for the creation of stop condition. [13] read the last byte of receive data. [14] clear rcvd. [15] set slave receive mode. [1] [2] [3] [4] [5] [6] [7] [8] [9] [11] [12] [13] clear stop in icsr [10] [14] [15] supplementary explanation: when one byte is received, steps [2] to [6] are skipped after step [1], before jumping to step [7]. the step [8] is dummy-read in icdrr. figure 15.18 sample flowch art for master receive mode
section 15 i 2 c bus interface 2 (iic2) rev.5.00 nov. 02, 2005 page 260 of 418 rej09b0028-0500 tdre=1 ? yes yes no slave transmit mode clear aas in icsr write transmit data in icdrt read tdre in icsr last byte? write transmit data in icdrt read tend in icsr clear tend in icsr clear trs in iccr1 to 0 dummy read icdrr clear tdre in icsr end [1] clear the aas flag. [2] set transmit data for icdrt (except for the last data). [3] wait for icdrt empty. [4] set the last byte of transmit data. [5] wait for the last byte to be transmitted. [6] clear the tend flag . [7] set slave receive mode. [8] dummy-read icdrr to release the scl line. [9] clear the tdre flag. no no yes tend=1 ? [1] [2] [3] [4] [5] [6] [7] [8] [9] figure 15.19 sample flowchart for slave transmit mode
section 15 i 2 c bus interface 2 (iic2) rev.5.00 nov. 02, 2005 page 261 of 418 rej09b0028-0500 supplementary explanation: when one byte is received, steps [2] to [6] are skipped after step [1], before jumping to step [7]. the step [8] is dummy-read in icdrr. no yes rdrf=1 ? no yes rdrf=1 ? last receive - 1? slave receive mode clear aas in icsr clear ackbt in icier to 0 dummy-read icdrr read rdrf in icsr read icdrr set ackbt in icier to 1 read icdrr read rdrf in icsr read icdrr end no yes [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [1] clear the aas flag. [2] set acknowledge to the transmit device. [3] dummy-read icdrr. [4] wait for 1 byte to be received. [5] check whether it is the (last receive - 1). [6] read the receive data. [7] set acknowledge of the last byte. [8] read the (last byte - 1) of receive data. [9] wait the last byte to be received. [10] read for the last byte of receive data. figure 15.20 sample flowch art for slave receive mode
section 15 i 2 c bus interface 2 (iic2) rev.5.00 nov. 02, 2005 page 262 of 418 rej09b0028-0500 15.5 interrupt request there are six interrupt requ ests in this module; transmit data em pty, transmit end, receive data full, nack receive, stop recogn ition, and arbitration lo st/overrun. table 15.3 shows the contents of each interrupt request. table 15.3 interrupt requests interrupt request abbreviat ion interrupt condition i 2 c mode clocked synchronous mode transmit data empty txi (tdre = 1) ? (tie = 1) { { transmit end tei (tend = 1) ? (teie = 1) { { receive data full rxi (rdrf = 1) ? (rie = 1) { { stop recognition stpi (stop = 1) ? (stie = 1) { nack receive { arbitration lost/overrun naki {(nackf = 1) + (al = 1)} ? (nakie = 1) { { when interrupt conditions described in table 15.3 are 1 and the i bit in ccr is 0, the cpu executes an interrupt exception pr ocessing. interrupt sources should be cleared in the exception processing. tdre and tend are automatically cl eared to 0 by writing the transmit data to icdrt. rdrf are automatically cl eared to 0 by readin g icdrr. tdre is set to 1 again at the same time when transmit data is wr itten to icdrt. when tdre is cleared to 0, then an excessive data of one byte may be transmitted.
section 15 i 2 c bus interface 2 (iic2) rev.5.00 nov. 02, 2005 page 263 of 418 rej09b0028-0500 15.6 bit synchronous circuit in master mode,this module has a possibility that hi gh level period may be short in the two states described below. ? when scl is driven to low by the slave device ? when the rising speed of scl is lowered by the load of the scl line (load capacitance or pull- up resistance) therefore, it monitors scl and communicates by bit with synchronization. figure 15.21 shows the timing of the bit synchronous circuit and table 15.4 shows the time when scl output changes from low to hi-z then scl is monitored. scl vih scl monitor timing reference clock internal scl figure 15.21 the timing of the bit synchronous circuit table 15.4 time for monitoring scl cks3 cks2 time for monitoring scl 0 7.5 tcyc 0 1 19.5 tcyc 0 17.5 tcyc 1 1 41.5 tcyc
section 15 i 2 c bus interface 2 (iic2) rev.5.00 nov. 02, 2005 page 264 of 418 rej09b0028-0500 15.7 usage notes 15.7.1 issue (retransmission) of start/stop conditions in master mode, when the start/stop conditions are issued (retransmitted) at the specific timing under the following condition 1 or 2, such conditions may not be output successfully. to avoid this, issue (retransmit) the start/s top conditions after the fall of th e ninth clock is confirmed. check the sclo bit in the i 2 c control register 2 (iicr2) to confirm the fall of the ninth clock. 1. when the rising of scl falls behind the time specified in section 17.6, bit synchronous circuit, by the load of the scl bus (l oad capacitance or pull-up resistance) 2. when the bit synchronous circuit is activated by extending the low period of eighth and ninth clocks, that is driven by the slave device 15.7.2 wait setting in i 2 c bus mode register (icmr) if the wait bit is set to 1, and the scl signal is dr iven low for two or more transfer clocks by the slave device at the eighth and ninth clocks, the high period of ninth clock may be shortened. to avoid this, set the wait bit in icmr to 0.
section 16 a/d converter adcms32a_000020020200 rev.5.00 nov. 02, 2005 page 265 of 418 rej09b0028-0500 section 16 a/d converter this lsi includes a successive approximation type 10-bit a/d converter that allows up to eight analog input channels to be selected. the block diagram of the a/d converter is shown in figure 16.1. 16.1 features ? 10-bit resolution ? eight input channels ? conversion time: at least 3.5 s per channel (at 20-mhz operation) ? two operating modes ? single mode: single-channel a/d conversion ? scan mode: continuous a/d conversion on 1 to 4 channels ? four data registers ? conversion results are held in a data register for each channel ? sample-and-hold function ? two conversion start methods ? software ? external trigger signal ? interrupt request ? an a/d conversion end interrupt request (adi) can be generated
section 16 a/d converter rev.5.00 nov. 02, 2005 page 266 of 418 rej09b0028-0500 module data bus control circuit internal data bus 10-bit d/a comparator + sample-and- hold circuit adi interrupt bus interface successive approximations register analog multiplexer a d c s r a d c r a d d r d a d d r c a d d r b a d d r a an0 an1 an2 an3 an4 an5 an6 an7 a/d control register a/d control/status register a/d data register a a/d data register b a/d data register c a/d data register d [legend] adcr: adcsr: addra: addrb: addrc: addrd: adtrg /4 /8 av cc figure 16.1 block di agram of a/d converter
section 16 a/d converter rev.5.00 nov. 02, 2005 page 267 of 418 rej09b0028-0500 16.2 input/output pins table 16.1 summarizes the input pins used by th e a/d converter. the 8 analog input pins are divided into two groups; analog input pins 0 to 3 (an0 to an3) comprising group 0, analog input pins 4 to 7 (an4 to an7) comprising group 1. the avcc pin is the power supply pin for the analog block in the a/d converter. table 16.1 pin configuration pin name abbreviation i/o function analog power supply pin av cc input analog block power supply analog input pin 0 an0 input analog input pin 1 an1 input analog input pin 2 an2 input analog input pin 3 an3 input group 0 analog input analog input pin 4 an4 input analog input pin 5 an5 input analog input pin 6 an6 input analog input pin 7 an7 input group 1 analog input a/d external trigger input pin adtrg input external trigger input for starting a/d conversion
section 16 a/d converter rev.5.00 nov. 02, 2005 page 268 of 418 rej09b0028-0500 16.3 register descriptions the a/d converter has the following registers. ? a/d data register a (addra) ? a/d data register b (addrb) ? a/d data register c (addrc) ? a/d data register d (addrd) ? a/d control/status register (adcsr) ? a/d control register (adcr) 16.3.1 a/d data registers a to d (addra to addrd) there are four 16-bit read-only addr registers; addra to addrd, used to store the results of a/d conversion. the addr registers, which st ore a conversion result for each analog input channel, are shown in table 16.2. the converted 10-bit data is stored in bits 15 to 6. the lower 6 bits are always read as 0. the data bus width between the cpu and the a/d converter is 8 bits. the upper byte can be read directly from the cpu, however the lower byte should be r ead via a temporary register. the temporary register cont ents are transferred from the addr when the upper byte data is read. therefore byte access to add r should be done by r eading the upper byte first then the lower one. word access is also possible. ad dr is initialized to h'0000. table 16.2 analog input channels and corresponding addr registers analog input channel group 0 group 1 a/d data register to be stored results of a/d conversion an0 an4 addra an1 an5 addrb an2 an6 addrc an3 an7 addrd
section 16 a/d converter rev.5.00 nov. 02, 2005 page 269 of 418 rej09b0028-0500 16.3.2 a/d control/status register (adcsr) adcsr consists of the control bits and conversion end status bits of the a/d converter. bit bit name initial value r/w description 7 adf 0 r/w a/d end flag [setting conditions] ? when a/d conversion ends in single mode ? when a/d conversion ends once on all the channels selected in scan mode [clearing condition] ? when 0 is written after reading adf = 1 6 adie 0 r/w a/d interrupt enable a/d conversion end interrupt request (adi) is enabled by adf when this bit is set to 1 5 adst 0 r/w a/d start setting this bit to 1 starts a/d conversion. in single mode, this bit is cleared to 0 automatically when conversion on the specified channel is complete. in scan mode, conversion continues sequentially on the specified channels until this bit is cleared to 0 by software, a reset, or a transition to standby mode. 4 scan 0 r/w scan mode selects single mode or scan mode as the a/d conversion operating mode. 0: single mode 1: scan mode 3 cks 0 r/w clock select selects the a/d conversions time. 0: conversion time = 134 states (max.) 1: conversion time = 70 states (max.) clear the adst bit to 0 before switching the conversion time.
section 16 a/d converter rev.5.00 nov. 02, 2005 page 270 of 418 rej09b0028-0500 bit bit name initial value r/w description 2 1 0 ch2 ch1 ch0 0 0 0 r/w r/w r/w channel select 2 to 0 select analog input channels. when scan = 0 when scan = 1 000: an0 000: an0 001: an1 001: an0 and an1 010: an2 010: an0 to an2 011: an3 011: an0 to an3 100: an4 100: an4 101: an5 101: an4 and an5 110: an6 110: an4 to an6 111: an7 111: an4 to an7 16.3.3 a/d control register (adcr) adcr enables a/d conversion started by an external trigger signal. bit bit name initial value r/w description 7 trge 0 r/w trigger enable a/d conversion is started at the falling edge and the rising edge of the external trigger signal ( adtrg ) when this bit is set to 1. the selection between the falling edge and rising edge of the external trigger pin ( adtrg ) conforms to the wpeg5 bit in the interrupt edge select register 2 (iegr2) 6 to 1 ? all 1 ? reserved these bits are always read as 1. 0 ? 0 r/w reserved do not set this bit to 1, though the bit is readable/writable.
section 16 a/d converter rev.5.00 nov. 02, 2005 page 271 of 418 rej09b0028-0500 16.4 operation the a/d converter operates by su ccessive approximation with 10-b it resolution. it has two operating modes; single mode and scan mode. when changing the operating mode or analog input channel, in order to prevent in correct operation, first clear th e bit adst in adcsr to 0. the adst bit can be set at the same time as the opera ting mode or analog input channel is changed. 16.4.1 single mode in single mode, a/d conversion is performed once for the analog input of the specified single channel as follows: 1. a/d conversion is started when the adst bit in adcsr is set to 1, according to software or external trigger input. 2. when a/d conversion is completed, the resu lt is transferred to the corresponding a/d data register of the channel. 3. on completion of conversion, the adf bit in adcsr is set to 1. if the adie bit is set to 1 at this time, an adi interrupt request is generated. 4. the adst bit remains set to 1 during a/d conversion. when a/d conversion ends, the adst bit is automatically cleared to 0 and the a/d converter enters the wait state. 16.4.2 scan mode in scan mode, a/d conversion is performed sequentially for the analog input of the specified channels (four channels maximum) as follows: 1. when the adst bit in adcsr is set to 1 by software or external trigger input, a/d conversion starts on the first channel in the group (an0 when ch2 = 0, an4 when ch2 = 1). 2. when a/d conversion for each channel is comple ted, the result is sequentially transferred to the a/d data register corresponding to each channel. 3. when conversion of all the selected channels is completed, the adf flag in adcsr is set to 1. if the adie bit is set to 1 at this time, an adi interrupt requested is generated. a/d conversion starts again on the first channel in the group. 4. the adst bit is not automatically cleared to 0. steps [2] and [3] are re peated as long as the adst bit remains set to 1. when the adst bi t is cleared to 0, a/ d conversion stops.
section 16 a/d converter rev.5.00 nov. 02, 2005 page 272 of 418 rej09b0028-0500 16.4.3 input sampling and a/d conversion time the a/d converter has a built-in sample-and-hold circuit. the a/d converter samples the analog input when the a/d conversion start delay time (t d ) has passed after the adst bit is set to 1, then starts conversion. figure 16.2 shows the a/d conversion timing. table 16.3 shows the a/d conversion time. as indicated in figure 16.2, th e a/d conversion time includes t d and the input sampling time. the length of t d varies depending on the timing of the wr ite access to adcsr. the total conversion time therefore varies w ithin the ranges indicated in table 16.3. in scan mode, the values given in table 16.3 apply to the first conversion time. in the second and subsequent conversions, the conversion time is 128 states (fixed) when cks = 0 and 66 states (fixed) when cks = 1. (1) (2) t d t spl t conv address write signal input sampling timing adf [legend] (1) : (2) : t d : t spl : t conv : adcsr write cycle adcsr address a/d conversion start delay time input sampling time a/d conversion time figure 16.2 a/d conversion timing
section 16 a/d converter rev.5.00 nov. 02, 2005 page 273 of 418 rej09b0028-0500 table 16.3 a/d conversio n time (single mode) cks = 0 cks = 1 item symbol min typ max min typ max a/d conversion start delay time t d 6 ? 9 4 ? 5 input sampling time t spl ? 31 ? ? 15 ? a/d conversion time t conv 131 ? 134 69 ? 70 note: all values represent the number of states. 16.4.4 external tr igger input timing a/d conversion can also be started by an external trigger input. when the trge bit in adcr is set to 1, external trigger input is enabled at the adtrg pin. a falling edge at the adtrg input pin sets the adst bit in adcsr to 1, starting a/d conversion. other operations, in both single and scan modes, are the same as when the bit adst has been set to 1 by software. figure 16.3 shows the timing. internal trigger signal adst a/d conversion figure 16.3 external trigger input timing
section 16 a/d converter rev.5.00 nov. 02, 2005 page 274 of 418 rej09b0028-0500 16.5 a/d conversion accuracy definitions this lsi's a/d conversion accuracy definitions are given below. ? resolution the number of a/d converter digital output codes ? quantization error the deviation inherent in the a/d converter, given by 1/2 lsb (see figure 16.4). ? offset error the deviation of the analog input voltage valu e from the ideal a/d conversion characteristic when the digital output changes from the minimum voltage value 0000000000 to 0000000001 (see figure 16.5). ? full-scale error the deviation of the analog input voltage valu e from the ideal a/d conversion characteristic when the digital output changes from 1111111110 to 1111111111 (see figure 16.5). ? nonlinearity error the deviation from the ideal a/d conversion charact eristic as the voltage changes from zero to full scale. this does not include the offset error, full-scale error, or quantization error. ? absolute accuracy the deviation between the digital value and the analog input value. includes offset error, full- scale error, quantization erro r, and nonlinearity error.
section 16 a/d converter rev.5.00 nov. 02, 2005 page 275 of 418 rej09b0028-0500 111 110 101 100 011 010 001 000 1 8 2 8 6 8 7 8 fs quantization error digital output ideal a/d conversion characteristic analog input voltage 3 8 4 8 5 8 figure 16.4 a/d conversio n accuracy definitions (1) fs digital output ideal a/d conversion characteristic nonlinearity error analog input voltage offset error actual a/d conversion characteristic full-scale error figure 16.5 a/d conversio n accuracy definitions (2)
section 16 a/d converter rev.5.00 nov. 02, 2005 page 276 of 418 rej09b0028-0500 16.6 usage notes 16.6.1 permissible si gnal source impedance this lsi's analog input is designed such that conv ersion accuracy is guarant eed for an input signal for which the signal source impedance is 5 k ? or less. this specification is provided to enable the a/d converter's sample-and-hold circuit input capacitance to be charged within the sampling time; if the sensor output impedance exceeds 5 k ? , charging may be insufficient and it may not be possible to guarantee a/d conversi on accuracy. however, for a/d co nversion in single mode with a large capacitance provided externally, the input load will essentially comprise only the internal input resistance of 10 k ? , and the signal source impedance is ignored. however, as a low-pass filter effect is obtained in this case, it may not be possible to follow an analog signal with a large differential coefficient (e.g., 5 mv/ s or greater) (see figure 16.6). when converting a high-speed analog signal or converting in scan mode, a low-impedance buffer should be inserted. 16.6.2 influences on absolute accuracy adding capacitance results in coupling with gn d, and therefore noise in gnd may adversely affect absolute accuracy. be sure to make the connection to an electrically stable gnd. care is also required to ensure that filter circuits do not interfere with digital signals or act as antennas on the mounting board. 20 pf 10 k ? c in = 15 pf sensor output impedance up to 5 k ? this lsi low-pass filter c to 0.1 f sensor input a/d converter equivalent circuit figure 16.6 analog input circuit example
section 17 eeprom rev.5.00 nov. 02, 2005 page 277 of 418 rej09b0028-0500 section 17 eeprom the h8/3694n has an on-chip 512-byte eeprom. the block diagram of the eeprom is shown in figure 17.1. 17.1 features ? two writing methods: 1-byte write page write: page size 8 bytes ? three reading methods: current address read random address read sequential read ? acknowledge polling possible ? write cycle time: 10 ms (power supply voltage vcc = 2.7 v or more) ? write/erase endurance: 10 4 cycles/byte (byte write mode), 10 5 cycles/page (page write mode) ? data retention: 10 years after the write cycle of 10 4 cycles (page write mode) ? interface with the cpu i 2 c bus interface (complies with the standard of philips corporation) device code 1010 sleep address code can be ch anged (initial value: 000) the i 2 c bus is open to the outside, so the eeprom can be directly accessed from the outside.
section 17 eeprom rev.5.00 nov. 02, 2005 page 278 of 418 rej09b0028-0500 h'0000 h'01ff h'ff09 h'ff10 esar sda eeprom data bus eeprom key register (ekr) key control circuit i 2 c bus interface control circuit address bus y decoder y-select/ sense amp. memory array user area (512 bytes) slave address register power-on reset booster circuit eeprom module esar: register for referring the slave address (specifies the slave address of the memory array) [legend] x decoder scl figure 17.1 block diagram of eeprom
section 17 eeprom rev.5.00 nov. 02, 2005 page 279 of 418 rej09b0028-0500 17.2 input/output pins pins used in the eeprom are listed in table 17.1. table 17.1 pin configuration pin name symbol input/output function serial clock pin scl input the scl pin is used to control serial input/output data timing. the data is input at the rising edge of the clock and output at the falling edge of the clock. the scl pin needs to be pulled up by resistor as that pin is open-drain driven structure of the i 2 c pin. use proper resistor value for your system by considering v ol , i ol , and the c in pin capacitance in section 21.2.2, dc characteristics and in section 21.2.3, ac characteristics. maximum clock frequency is 400 khz. serial data pin sda input/output the sda pin is bidirectional for serial data transfer. the sda pin needs to be pulled up by resistor as that pin is open-drain driven structure. use proper resistor value for your system by considering v ol , i ol , and the c in pin capacitance in section 21.2.2, dc characteristics and in section 21.2.3, ac characteristics. except for a start condition and a stop condition which will be discussed later, the high- to-low and low-to-high change of sda input should be done during scl low periods. 17.3 register description the eeprom has a following register. ? eeprom key register (ekr) 17.3.1 eeprom key register (ekr) ekr is an 8-bit readable/writable register, whic h changes the slave address code written in the eeprom. the slave address code is changed by writing h'5f in ekr and then writing either of h'00 to h'07 as an address code to the h'ff09 address in the eeprom by the byte write method. ekr is initialized to h'ff.
section 17 eeprom rev.5.00 nov. 02, 2005 page 280 of 418 rej09b0028-0500 17.4 operation 17.4.1 eeprom interface the hd64n3694g has a multi-chip structure with two internal chips of the hd64f3694g (f- ztat? version) and 512-byte eeprom. the HD6483694G has a multi-chip structure with two internal chips of the hd6433694g (mask-rom version) and 512-byte eeprom. the eeprom interface is the i 2 c bus interface. this i 2 c bus is open to th e outside, so the communication with the external devices connected to the i 2 c bus can be made. 17.4.2 bus format and timing the i 2 c bus format and the i 2 c bus timing follow section 15.4.1, i 2 c bus format. the bus formats specific for the eeprom ar e the following two. 1. the eeprom address is configured of two bytes, the write data is transferred in the order of upper address and lower address from each msb side. 2. the write data is transmitted from the msb side. the bus format and bus timing of the eeprom are shown in figure 17.2. r/ w ack scl sda start condition slave address upper memory address lower memory address data data stop conditon [legend] r/ w : r/ w code (0 is for a write and 1 is for a read), ack: acknowledge ack ack ack ack 11 2345678 a15 a8 a7 a0 d7 d0 d7 d0 91 89 1 89 1 89 8 9 figure 17.2 eeprom bus format and bus timing 17.4.3 start condition a high-to-low transition of the sda input with the scl input high is needed to generate the start condition for starting read, write operation.
section 17 eeprom rev.5.00 nov. 02, 2005 page 281 of 418 rej09b0028-0500 17.4.4 stop condition a low-to-high transition of the sda input with the scl input high is needed to generate the stop condition for stopping read, write operation. the standby operation starts after a read sequen ce by a stop condition. in the case of write operation, a stop condition terminat es the write data inputs and pl ace the device in an internally- timed write cycle to the memories. after the internally-timed write cycle (t wc ) which is specified as t wc , the device enters a standby mode. 17.4.5 acknowledge all address data and serial data su ch as read data and write data are transmitted to and from in 8- bit unit. the acknowledgement is the signal that indicates that this 8-bit data is normally transmitted to and from. in the write operation, eeprom sends "0" to ac knowledge in the ninth cy cle after receiving the data. in the read operation, eeprom sends a read data following the acknowledgement after receiving the data. after sending read data, the eeprom enters the bus open state. if the eeprom receives "0" as an acknowle dgement, it sends read data of the next address. if the eeprom does not receive acknowledgement "0" and receives a fo llowing stop cond ition, it stops the read operation and enters a standby mode. if the eeprom receives neither acknowledgement "0" nor a stop condition, the eeprom keeps bus open without sending read data. 17.4.6 slave addressing the eeprom device receives a 7-b it slave address and a 1-bit r/ w code following the generation of the start conditions. the eeprom enables the ch ip for a read or a write operation with this operation. the slave address consists of a former 4-bit device code and latter 3-bit slave address as shown in table 17.2. the device code is used to distinguish device type and this lsi uses "1010" fixed code in the same manner as in a general-purpose eepro m. the slave address code selects one device out of all devices with device code 1010 (8 devices in maximum) which are connected to the i 2 c bus. this means that the device is selected if the inputted slave address code received in the order of a2, a1, a0 is equal to th e corresponding slave address reference register (esar). the slave address code is stored in the address h'ff09 in the eeprom. it is transferred to esar from the slave address register in the memory arra y during 10 ms after the reset is released. an access to the eeprom is not allowed during transfer.
section 17 eeprom rev.5.00 nov. 02, 2005 page 282 of 418 rej09b0028-0500 the initial value of the slave address code written in the eeprom is h'00. it can be written in the range of h'00 to h'07. be sure to write the data by the byte write method. the next one bit of the slave address is the r/ w code. 0 is for a write and 1 is for a read. the eeprom turns to a standby state if the devi ce code is not "1010" or slave address code doesn?t coincide. table 17.2 slave addresses bit bit name initial value setting value remarks 7 device code d3 ? 1 6 device code d2 ? 0 5 device code d1 ? 1 4 device code d0 ? 0 3 slave address code a2 0 a2 the initial value can be changed 2 slave address code a1 0 a1 the initial value can be changed 1 slave address code a0 0 a0 the initial value can be changed
section 17 eeprom rev.5.00 nov. 02, 2005 page 283 of 418 rej09b0028-0500 17.4.7 write operations there are two types write operati ons; byte write operation and page write operation. to initiate the write operation, input 0 to r/ w code following the slave address. 1. byte write a write operation requires an 8-bit data of a 7-bit slave address with r/ w code = "0". then the eeprom sends acknowledgement "0" at the ninth bit. this enters the write mode. then, two bytes of the memory address are received fr om the msb side in the order of upper and lower. upon receipt of one-b yte memory address, the eepr om sends acknowledgement "0" and receives a following a one-byte write data. after receipt of write data, the eeprom sends acknowledgement "0". if the eeprom receives a stop c ondition, the eeprom enters an internally controlled write cycle and termin ates receipt of scl and sda inputs until completion of the write cycle. the eeprom re turns to a standby mode after completion of the write cycle. the byte write operation is shown in figure 17.3. r/ w ack scl sda ack ack ack 11 2345678 a15 a8 a7 a0 d7 d0 91 89 1 89 8 9 start condition upper memory address lower memory address write data slave address stop conditon [legend] r/ w : r/ w code (0 is for a write and 1 is for a read) ack: acknowledge figure 17.3 byte write operation 2. page write this lsi is capable of the page write operation which allows any number of bytes up to 8 bytes to be written in a single write cycle. the write data is input in the same sequence as the byte write in the order of a start condition, slave address + r/ w code, memory address (n), and write data (dn) with every ninth bit acknowledgement "0" output. the eeprom enters the page write operation if the eeprom receives mo re write data (dn+1) is input instead of receiving a stop condition after receiving the write data (dn). lsb 3 bits (a2 to a0) in the eeprom address are automatically incremented to be the (n+1) address upon receiving write data (dn+1). thus the write data can be received sequentially.
section 17 eeprom rev.5.00 nov. 02, 2005 page 284 of 418 rej09b0028-0500 addresses in the page are incremented at each r eceipt of the write data and the write data can be input up to 8 bytes. if the lsb 3 bits (a 2 to a0) in the eeprom address reach the last address of the page, the address will roll over to the first address of the same page. when the address is rolled over, write data is received tw ice or more to the same address, however, the last received data is valid. at the receipt of the stop condition, write data reception is terminated and the write operation is entered. the page write operation is shown in figure 17.4. scl sda 11 2345678 a15 a8 a7 a0 d7 d0 d7 d0 91 89 1 89 8 9 r/ w ack ack ack ack ack start condition upper memory address lower memory address write data write data stop conditon [legend] slave address r/ w : r/ w code (0 is for a write and 1 is for a read), ack: acknowledge figure 17.4 page write operation 17.4.8 acknowledge polling acknowledge polling feature is used to show if the eeprom is in an internally-timed write cycle or not. this feature is initiated by the input of the 8-bit slave address + r/ w code following the start condition during an internally-timed write cycle. acknowledge polling will operate r/w code = "0". the ninth acknowledgement judges if the eeprom is an intern ally-timed write cycle or not. acknowledgement "1" shows the eeprom is in a internally-timed write cycle and acknowledgement "0" shows the internally-timed write cycle has been completed. the acknowledge polling starts to function after a write da ta is input, i.e., when the stop condition is input.
section 17 eeprom rev.5.00 nov. 02, 2005 page 285 of 418 rej09b0028-0500 17.4.9 read operation there are three read operations; current address re ad, random address read, and sequential read. read operations are initiated in the same way as write operations with the exception of r/w = 1. 1. current address read the internal address counter maintains the (n+1) address that is made by the last address (n) accessed during the last read or write operation, with incremented by one. current address read accesses the (n+1) address kept by the internal address counter. after receiving in the order of a star t condition and the slave address + r/ w code (r/w = 1), the eeprom outputs the 1-byte data of the (n+1) address from the most significant bit following acknowledgement "0". if the eepro m receives in the orde r of acknowledgement "1" and a following stop condition, the eeprom stops the read operation and is turned to a standby state. in case the eeprom has accessed the last addr ess h'01ff at previous read operation, the current address will roll over and returns to zero address. in case the eeprom has accessed the last address of the page at previous write ope ration, the current address will roll over within page addressing and returns to the first address in the same page. the current address is valid while power is on . the current address after power on will be undefined. after power is turned on, define the address by the random address read operation described below is necessary. the current address read operation is shown in figure 17.5. r/ w sda d7 d0 ack scl ack 11 23456789 8 9 start condition stop conditon [legend] r/ w : r/ w code (0 is for a write and 1 is for a read) ack: acknowledge read data slave address figure 17.5 current address read operation
section 17 eeprom rev.5.00 nov. 02, 2005 page 286 of 418 rej09b0028-0500 2. random address read this is a read operation with defined read address. a random address read requires a dummy write to set read address. the eeprom re ceives a start condition, slave address + r/ w code (r/ w = 0), memory address (upper) and memory address (lower) sequentially. the eeprom outputs acknowledgement "0" after receiving memory address (low er) then enters a current address read with receiving a start condition again. the eepro m outputs the read data of the address which was defined in the dummy write operation. after receiving acknowledgement "1" and a following stop condition, the eeprom stops the random read operation and returns to a standby state. the random address read operation is shown in figure 17.6. sda a15 a8 a7 a0 d7 d0 r/ w ack scl ack ack 11 23456789 1 89 89 11 23456789 8 9 rack ack start condition start condition upper memory address lower memory address read data stop conditon [legend] slave address slave address r/ w : r/ w code (0 is for a write and 1 is for a read), ack: acknowledge figure 17.6 random address read operation 3. sequential read this is a mode to read the data sequentially. da ta is sequential read by either a current address read or a random address read. if the eepr om receives acknowledgem ent "0" after 1-byte read data is output, the read address is incremented and the next 1-byte read data are coming out. data is output sequentially by incremen ting addresses as long as the eeprom receives acknowledgement "0" after the data is output. the address will roll over and returns address zero if it reaches the last address h'01ff. the sequ ential read can be continued after roll over. the sequential read is terminated if th e eeprom receives acknowledgement "1" and a following stop condition as the same manner as in the random address read. the condition of a sequential read when the current address read is used is shown in figure 17.7.
section 17 eeprom rev.5.00 nov. 02, 2005 page 287 of 418 rej09b0028-0500 scl 11 23456789 89 1 8 9 sda d7 d0 d7 d0 r/ w ack ack ack start condition stop conditon [legend] r/ w : r/ w code (0 is for a write and 1 is for a read) ack: acknowledge read data read data slave address figure 17.7 sequential read operation (when current address read is used)
section 17 eeprom rev.5.00 nov. 02, 2005 page 288 of 418 rej09b0028-0500 17.5 usage notes 17.5.1 data protection at v cc on/off when v cc is turned on or off, the data might be destroyed by malfunction. be careful of the notices described below to prevent the data to be destroyed. 1. scl and sda should be fixed to v cc or v ss during v cc on/off. 2. v cc should be turned off after the eep rom is placed in a standby state. 3. when v cc is turned on from the intermediate level, malfunction is caused, so v cc should be turned on from the ground level (v ss ). 4. v cc turn on speed should be longer than 10 us. 17.5.2 write/erase endurance the endurance is 10 5 cycles/page (1% cumulative failure ra te) in case of page programming and 10 4 cycles/byte in case of byte programming. the data retention time is more than 10 years when a device is page-programmed less than 10 4 cycles. 17.5.3 noise suppression time this eeprom has a noise suppression function at scl and sda inputs, that cuts noise of width less than 50 ns. be careful not to allow noise of width more than 50 ns because the noise of with more than 50 ms is rec ognized as an active pulse.
section 18 power-on reset and low-v oltage detection ci rcuits (optional) lvi0000a_000020030300 rev.5.00 nov. 02, 2005 page 289 of 418 rej09b0028-0500 section 18 power-on reset and low-voltage detection circuits (optional) this lsi can include a power-on re set circuit and low-voltage detect ion circuit as optional circuits. the low-voltage detection circuit consists of two circuits: lvdi (interrupt by low voltage detect) and lvdr (reset by low voltage detect) circuits. this circuit is used to prevent abnormal opera tion (runaway execution) from occurring due to the power supply voltage fall and to recreate the state before the power supply voltage fall when the power supply voltage rises again. even if the power supply voltage falls, the unstable state when the power supply voltage falls below the guaranteed operating voltage can be removed by entering standby mode when exceeding the guaranteed operating voltage and during normal operat ion. thus, system stability can be improved. if the power supply voltage falls more, the reset state is automatically entered. if the power supply voltage rises again, the reset state is held for a specified period, then active mode is automatically entered. figure 18.1 is a block diagram of the power-on re set circuit and the low-vo ltage detection circuit. 18.1 features ? power-on reset circuit uses an external capacitor to generate an internal reset signal when power is first supplied. ? low-voltage detection circuit lvdr: monitors the power-supply voltage, and generates an internal reset signal when the voltage falls below a specified value. lvdi: monitors the power-supply voltage, and generates an interrupt when the voltage falls below or rises above resp ective specified values. two pairs of detection levels for reset generation voltage are available: when only the lvdr circuit is used, or when the lvdi and lvdr circuits are both used.
section 18 power-on reset and low-v oltage detection ci rcuits (optional) rev.5.00 nov. 02, 2005 page 290 of 418 rej09b0028-0500 pss: lvdcr: lvdsr: lvdres : lvdint : vreset: vint: prescaler s low-voltage-detection control register low-voltage-detection status register low-voltage-detection reset signal low-voltage-detection interrupt signal reset detection voltage power-supply fall/rise detection voltage [legend] res c res ck r pss r s q ovf vreset vcc vint lvdres lvdcr lvdsr lvdint reference voltage generator noise canceler noise canceler interrupt control circuit internal reset signal power-on reset circuit low-voltage detection circuit internal data bus ladder resistor + ? + ? interrupt request figure 18.1 block diagram of power-on reset circuit and low-voltage detection circuit 18.2 register descriptions the low-voltage detection circu it has the following registers. ? low-voltage-detection control register (lvdcr) ? low-voltage-detection status register (lvdsr) 18.2.1 low-voltage-detection control register (lvdcr) lvdcr is used to enable or disable the low-voltage detection circuit, set the detection levels for the lvdr function, enable or disable the lvdr function, and enable or disable generation of an interrupt when the power-supply voltage rises above or falls below the respective levels.
section 18 power-on reset and low-v oltage detection ci rcuits (optional) rev.5.00 nov. 02, 2005 page 291 of 418 rej09b0028-0500 table 18.1 shows the relationship between the lvdcr settings and select functions. lvdcr should be set according to table 18.1. bit bit name initial value r/w description 7 lvde 0 * r/w lvd enable 0: the low-voltage detection circuit is not used (in standby mode) 1: the low-voltage detection circuit is used 6 to 4 ? all 1 ? reserved these bits are always read as 1, and cannot be modified. 3 lvdsel 0 * r/w lvdr detection level select 0: reset detection voltage is 2.3 v (typ.) 1: reset detection voltage is 3.6 v (typ.) when the falling or rising voltage detection interrupt is used, reset detection voltage of 2.3 v (typ.) should be used. when only a reset detection interrupt is used, reset detection voltage of 3.6 v (typ.) should be used. 2 lvdre 0 * r/w lvdr enable 0: disables the lvdr function 1: enables the lvdr function 1 lvdde 0 r/w voltage-fall-interrupt enable 0: interrupt on the power-supply voltage falling below the selected detection level disabled 1: interrupt on the power-supply voltage falling below the selected detection level enabled 0 lvdue 0 r/w voltage-rise-interrupt enable 0: interrupt on the power-supply voltage rising above the selected detection level disabled 1: interrupt on the power-supply voltage rising above the selected detection level enabled note: * not initialized by lvdr but initialized by a power-on reset or wdt reset.
section 18 power-on reset and low-v oltage detection ci rcuits (optional) rev.5.00 nov. 02, 2005 page 292 of 418 rej09b0028-0500 table 18.1 lvdcr setting s and select functions lvdcr settings select functions lvde lvdsel lvdre lvdde lvdue power-on reset lvdr low-voltage- detection falling interrupt low-voltage- detection rising interrupt 0 * * * * o ? ? ? 1 1 1 0 0 o o ? ? 1 0 0 1 0 o ? o ? 1 0 0 1 1 o ? o o 1 0 1 1 1 o o o o legend: *: means invalid. 18.2.2 low-voltage-detection status register (lvdsr) lvdsr indicates whether the power-supply voltage falls below or rises above the respective specified values. bit bit name initial value r/w description 7 to 2 ? all 1 ? reserved these bits are always read as 1, and cannot be modified. 1 lvddf 0 * r/w lvd power-supply voltage fall flag [setting condition] when the power-supply voltage falls below vint (d) (typ. = 3.7 v) [clearing condition] writing 0 to this bit after reading it as 1 0 lvduf 0 * r/w lvd power-supply voltage rise flag [setting condition] when the power supply voltage falls below vint (d) while the lvdue bit in lvdcr is set to 1, then rises above vint (u) (typ. = 4.0 v) before falling below vreset1 (typ. = 2.3 v) [clearing condition] writing 0 to this bit after reading it as 1 note: * initialized by lvdr.
section 18 power-on reset and low-v oltage detection ci rcuits (optional) rev.5.00 nov. 02, 2005 page 293 of 418 rej09b0028-0500 18.3 operation 18.3.1 power-on reset circuit figure 18.2 shows the timing of the operation of the power-on reset circuit. as the power-supply voltage rises, the capacitor which is externally c onnected to the res pin is gradually charged via the on-chip pull-up resistor (typ. 150 k ? ). since the state of the res pin is transmitted within the chip, the prescaler s and the en tire chip are in their reset states. when the level on the res pin reaches the specified value, the pr escaler s is released from its re set state and it starts counting. the ovf signal is generated to release the intern al reset signal after the prescaler s has counted 131,072 clock ( ) cycles. the noise cancellation circuit of approximately 100 ns is incorporated to prevent the incorrect operation of the chip by noise on the res pin. to achieve stable operation of this lsi, the power supply needs to rise to its full level and settles within the specified time. the maximum time required for the power supply to rise and settle after power has been supplied (t pwon ) is determined by the oscillation frequency (f osc ) and capacitance which is connected to res pin (c res ). if t pwon means the time requ ired to reach 90 % of power supply voltage, the power supply circuit should be designed to satisfy the following formula. t pwon (ms) 90 c res ( f) + 162/f osc (mhz) (t pwon 3000 ms, c res 0.22 f, and f osc = 10 in 2-mhz to 10-mhz operation) note that the power supply voltage (vcc) must fall below vpor = 100 mv and rise after charge on the res pin is removed. to remove charge on the res pin, it is recommended that the diode should be placed near vcc. if the power supply vo ltage (vcc) rises from the point above vpor, a power-on reset may not occur.
section 18 power-on reset and low-v oltage detection ci rcuits (optional) rev.5.00 nov. 02, 2005 page 294 of 418 rej09b0028-0500 res vcc pss-reset signal internal reset signal vss vss ovf 131,072 cycles pss counter starts reset released t pwon vpor figure 18.2 operational timi ng of power-on reset circuit 18.3.2 low-voltage detection circuit lvdr (reset by low voltage detect) circuit: figure 18.3 shows the timing of the lvdr function. the lvdr enters the module-standby state after a power-on reset is canceled. to operate th e lvdr, set the lvde bit in lvdcr to 1, wait for 50 s (t lvdon ) until the reference voltage and the low-voltage-detection power supply have stabilized by a software timer, etc., then set the lvdre bit in lvdcr to 1. after that, the output settings of ports must be made. to cancel the low-voltage detection circuit, first the lvdre bit should be cleared to 0 and then the lvde bit should be cleared to 0. the lvde and lvdre bits must not be cleared to 0 simultaneously because incorrect operation may occur. when the power-supply voltage falls below the vreset voltage (typ. = 2.3 v or 3.6 v), the lvdr clears the lvdres signal to 0, and resets the prescaler s. the low-voltage detection reset state remains in place until a power-on reset is generated. when the power-supply voltage rises above the vreset voltage again, the prescaler s starts counting. it counts 131,072 clock ( ) cycles, and then releases the internal reset signal. in th is case, the lvde, lvdsel, and lvdre bits in lvdcr are not initialized. note that if the power supply voltage (vcc) falls below v lvdrmin = 1.0 v and then rises from that point, the low-voltage detection reset may not occur. if the power supply voltage (vcc) falls below vpor = 100 mv, a power-on reset occurs.
section 18 power-on reset and low-v oltage detection ci rcuits (optional) rev.5.00 nov. 02, 2005 page 295 of 418 rej09b0028-0500 lvdres v cc vreset v ss v lvdrmin ovf pss-reset signal internal reset signal 131,072 cycles pss counter starts reset released figure 18.3 operational timing of lvdr circuit lvdi (interrupt by low voltage detect) circuit: figure 18.4 shows the timing of lvdi functions. the lvdi enters the module-standby state after a power-on reset is canceled. to operate the lvdi, set the lvde bit in lvdcr to 1, wait for 50 s (t lvdon ) until the reference voltage and the low-voltage-detection power supply have stabilized by a software timer, etc., then set the lvdde an d lvdue bits in lvdcr to 1. after that, the output settings of ports must be made. to cancel the low-voltage detection circuit, first the lvdde and lvdue bits should all be cleared to 0 and then the lvde bit should be cleared to 0. the lvde bit must not be cleared to 0 at the same timing as the lvdde and lvdue bits because incorrect operation may occur. when the power-supply voltage falls below vint (d) (typ. = 3.7 v) voltage, the lvdi clears the lvdint signal to 0 and the lvddf bit in lvdsr is set to 1. if the lvdde bit is 1 at this time, an irq0 interrupt request is simultaneously generated. in this case, the necessary data must be saved in the external eeprom, etc, and a transiti on must be made to standby mode or subsleep mode. until this processing is completed, the power supply voltage must be higher than the lower limit of the guaranteed operating voltage. when the power-supply voltage does not fall below vreset1 (typ. = 2.3 v) voltage but rises above vint (u) (typ. = 4.0 v) voltage, the lvdi sets the lvdint signal to 1. if the lvdue bit is 1 at
section 18 power-on reset and low-v oltage detection ci rcuits (optional) rev.5.00 nov. 02, 2005 page 296 of 418 rej09b0028-0500 this time, the lvduf bit in lvdsr is set to 1 and an irq0 interrupt request is simultaneously generated. if the power supply voltage (vcc) falls below vreset1 (typ. = 2.3 v) voltage, the lvdr function is performed. lvdint vcc vint (d) vint (u) vss lvddf lvdue lvduf irq0 interrupt generated irq0 interrupt generated lvdde vreset1 figure 18.4 operational timing of lvdi circuit
section 18 power-on reset and low-v oltage detection ci rcuits (optional) rev.5.00 nov. 02, 2005 page 297 of 418 rej09b0028-0500 procedures for clearing settin gs when using lvdr and lvdi: to operate or release the low-vo ltage detection circuit normally, follow the procedure described below. figure 18.5 shows the timing for the operation and release of the low-voltage detection circuit. 1. to operate the lo w-voltage detection circuit, set the lvde bit in lvdcr to 1. 2. wait for 50 s (t lvdon ) until the reference voltage and the low-voltage-detection power supply have stabilized by a software timer, etc. th en, clear the lvddf and lvduf bits in lvdsr to 0 and set the lvdre, lvdde, and lvdue bits in lvdcr to 1, as required. 3. to release the low-voltage detection circuit, start by clearing all of the lvdre, lvdde, and lvdue bits to 0. then clear the lvde bit to 0. the lvde bit must not be cleared to 0 at the same timing as the lvdre, lvdde, and lvdue bits because incorrect operation may occur. lvdre lvdde lvdue t lv d o n lvde figure 18.5 timing for operation/rel ease of low-voltage detection circuit
section 18 power-on reset and low-v oltage detection ci rcuits (optional) rev.5.00 nov. 02, 2005 page 298 of 418 rej09b0028-0500
section 19 power supply circuit psckt00a_000020020200 rev.5.00 nov. 02, 2005 page 299 of 418 rej09b0028-0500 section 19 power supply circuit this lsi incorporates an internal power supply step-down circuit. use of this circuit enables the internal power supply to be fixed at a constant level of approximately 3.0 v, independently of the voltage of the power supply connected to the external v cc pin. as a result, the current consumed when an external power supply is used at 3.0 v or above can be held down to virtually the same low level as when used at approxim ately 3.0 v. if the external power supply is 3.0 v or below, the internal voltage will be practically the same as the external voltage. it is, of course, also possible to use the same level of external power supply voltage and internal power supply voltage without using the internal power supply step-down circuit. 19.1 when using internal power supply step-down circuit connect the external po wer supply to the v cc pin, and connect a capacita nce of approximately 0.1 f between v cl and v ss , as shown in figure 19.1. the internal step-down circuit is made effective simply by adding this external circuit. in the ex ternal circuit interface, th e external power supply voltage connected to v cc and the gnd potential connected to v ss are the reference levels. for example, for port input/output levels, the v cc level is the reference for the high level, and the v ss level is that for the low level. the a/d converter analog power supply is not affected by the internal step-down circuit. v cl v ss internal logic step-down circuit internal power supply stabilization capacitance (approx. 0.1 f) v cc v cc = 3.0 to 5.5 v figure 19.1 power supply connection when internal step-down circuit is used
section 19 power supply circuit rev.5.00 nov. 02, 2005 page 300 of 418 rej09b0028-0500 19.2 when not using internal power supply step-down circuit when the internal power supply step-down circuit is not used, connect the external power supply to the v cl pin and v cc pin, as shown in figure 19.2. the external power supply is then input directly to the internal power supply. the permissible range for the power supply voltage is 3.0 v to 3.6 v. operation cannot be guaranteed if a voltage outside this range (less than 3.0 v or more than 3.6 v) is input. v cl v ss internal logic step-down circuit internal power supply v cc v cc = 3.0 to 3.6 v figure 19.2 power supply connection when internal step-down circuit is not used
section 20 list of registers rev.5.00 nov. 02, 2005 page 301 of 418 rej09b0028-0500 section 20 list of registers the register list gives information on the on-chip i/o register addresses, how the register bits are configured, and the register states in each operating mode. the information is given as shown below. 1. register addresses (address order) ? registers are listed from the lower allocation addresses. ? the symbol ? in the register-name column represents a reserved address or range of reserved addresses. do not attempt to access reserved addresses. ? when the address is 16-bit wide, the address of the upper byte is given in the list. ? registers are classified by functional modules. ? the data bus width is indicated. ? the number of access states is indicated. 2. register bits ? bit configurations of the registers are described in the same order as the register addresses. ? reserved bits are indicated by ? in the bit name column. ? when registers consist of 16 bits, bits are described from the msb side. 3. register states in each operating mode ? register states are described in the sa me order as the register addresses. ? the register states described here are for the basic operating mode s. if there is a specific reset for an on-chip peripheral module, refer to th e section on that on-chip peripheral module.
section 20 list of registers rev.5.00 nov. 02, 2005 page 302 of 418 rej09b0028-0500 20.1 register addresses (address order) the data-bus width column indicates the numb er of bits. the access-st ate column shows the number of states of the sel ected basic clock that is requi red for access to the register. note: access to undefined or reserved addresses should not take place. co rrect operation of the access itself or later operations is not guara nteed when such a register is accessed. register name abbre- viation bit no address module name data bus width access state ? ? ? h'f000 to h'f72f ? ? ? low-voltage detection control register lvdcr 8 h'f730 lvdc * 1 8 2 low-voltage detection status register lvdsr 8 h'f731 lvdc * 1 8 2 ? ? ? h'f732 to h'f747 ? ? ? i 2 c bus control register 1 iccr1 8 h'f748 iic2 8 2 i 2 c bus control register 2 iccr2 8 h'f749 iic2 8 2 i 2 c bus mode register icmr 8 h'f74a iic2 8 2 i 2 c bus interrupt enable register icier 8 h'f74b iic2 8 2 i 2 c bus status register icsr 8 h'f74c iic2 8 2 slave address register sar 8 h'f74d iic2 8 2 i 2 c bus transmit data register icdrt 8 h'f74e iic2 8 2 i 2 c bus receive data register icdrr 8 h'f74f iic2 8 2 ? ? ? h'f750 to h'ff7f ? ? ? timer mode register w tmrw 8 h'ff80 timer w 8 2 timer control register w tcrw 8 h'ff81 timer w 8 2 timer interrupt enable register w tierw 8 h'ff82 timer w 8 2 timer status register w tsrw 8 h'ff83 timer w 8 2 timer i/o control register 0 tior0 8 h'ff84 timer w 8 2 timer i/o control register 1 tior1 8 h'ff85 timer w 8 2 timer counter tcnt 16 h'ff86 timer w 16 * 2 2 general register a gra 16 h'ff88 timer w 16 * 2 2
section 20 list of registers rev.5.00 nov. 02, 2005 page 303 of 418 rej09b0028-0500 register name abbre- viation bit no address module name data bus width access state general register b grb 16 h'ff8a timer w 16 * 2 2 general register c grc 16 h'ff8c timer w 16 * 2 2 general register d grd 16 h'ff8e timer w 16 * 2 2 flash memory control register 1 flmcr1 8 h'ff90 rom 8 2 flash memory control register 2 flmcr2 8 h'ff91 rom 8 2 flash memory power control register flpwcr 8 h'ff92 rom 8 2 erase block register 1 ebr1 8 h'ff93 rom 8 2 ? ? ? h'ff94 to h'ff9a ? ? ? flash memory enable regist er fenr 8 h'ff9b rom 8 2 ? ? ? h'ff9c to h'ff9f ? ? ? timer control register v0 tcrv0 8 h'ffa0 timer v 8 3 timer control/status register v tcsrv 8 h'ffa1 timer v 8 3 timer constant register a tcora 8 h'ffa2 timer v 8 3 timer constant register b tcorb 8 h'ffa3 timer v 8 3 timer counter v tcntv 8 h'ffa4 timer v 8 3 timer control register v1 tcrv1 8 h'ffa5 timer v 8 3 timer mode register a tma 8 h'ffa6 timer a 8 2 timer counter a tca 8 h'ffa7 timer a 8 2 serial mode register smr 8 h'ffa8 sci3 8 3 bit rate register brr 8 h'ffa9 sci3 8 3 serial control register 3 scr3 8 h'ffaa sci3 8 3 transmit data register tdr 8 h'ffab sci3 8 3 serial status register ssr 8 h'ffac sci3 8 3 receive data register rdr 8 h'ffad sci3 8 3 ? ? ? h'ffae, h'ffaf ? ? ? a/d data register a addra 16 h'ffb0 a/d converter 8 3
section 20 list of registers rev.5.00 nov. 02, 2005 page 304 of 418 rej09b0028-0500 register name abbre- viation bit no address module name data bus width access state a/d data register b addrb 16 h'ffb2 a/d converter 8 3 a/d data register c addrc 16 h'ffb4 a/d converter 8 3 a/d data register d addrd 16 h'ffb6 a/d converter 8 3 a/d control/status regi ster adcsr 8 h'ffb8 a/d converter 8 3 a/d control register adcr 8 h'ffb9 a/d converter 8 3 ? ? ? h'ffba to h'ffbf ? ? ? timer control/status register wd tcsrw d 8 h'ffc0 wdt * 3 8 2 timer counter wd tcwd 8 h'ffc1 wdt * 3 8 2 timer mode register wd tmwd 8 h'ffc2 wdt * 3 8 2 ? ? ? h'ffc3 ? ? ? ? ? ? h'ffc4 to h'ffc7 ? ? ? address break control regist er abrkcr 8 h'ffc8 address break 8 2 address break status regi ster abrksr 8 h'ffc9 address break 8 2 break address register h barh 8 h'ffca address break 8 2 break address register l barl 8 h'ffcb address break 8 2 break data register h bdrh 8 h'ffcc address break 8 2 break data register l bdrl 8 h'ffcd address break 8 2 ? ? ? h'ffce, h'ffcf ? ? ?
section 20 list of registers rev.5.00 nov. 02, 2005 page 305 of 418 rej09b0028-0500 register name abbre- viation bit no address module name data bus width access state port pull-up control register 1 pucr1 8 h'ffd0 i/o port 8 2 port pull-up control register 5 pucr5 8 h'ffd1 i/o port 8 2 ? ? ? h'ffd2, h'ffd3 i/o port ? ? port data register 1 pdr1 8 h'ffd4 i/o port 8 2 port data register 2 pdr2 8 h'ffd5 i/o port 8 2 ? ? 8 h'ffd6, h'ffd7 i/o port ? ? port data register 5 pdr5 8 h'ffd8 i/o port 8 2 ? ? ? h'ffd9 i/o port ? ? port data register 7 pdr7 8 h'ffda i/o port 8 2 port data register 8 pdr8 8 h'ffdb i/o port 8 2 ? ? ? h'ffdc i/o port ? ? port data register b pdrb 8 h'ffdd i/o port 8 2 ? ? ? h'ffde, h'ffdf i/o port ? ? port mode register 1 pmr1 8 h'ffe0 i/o port 8 2 port mode register 5 pmr5 8 h'ffe1 i/o port 8 2 ? ? ? h'ffe2, h'ffe3 i/o port ? ? port control register 1 pcr1 8 h'ffe4 i/o port 8 2 port control register 2 pcr2 8 h'ffe5 i/o port 8 2 ? ? ? h'ffe6, h'ffe7 i/o port ? ? port control register 5 pcr5 8 h'ffe8 i/o port 8 2 ? ? ? h'ffe9 i/o port ? ? port control register 7 pcr7 8 h'ffea i/o port 8 2 port control register 8 pcr8 8 h'ffeb i/o port 8 2 ? ? ? h'ffec to h'ffef i/o port ? ?
section 20 list of registers rev.5.00 nov. 02, 2005 page 306 of 418 rej09b0028-0500 register name abbre- viation bit no address module name data bus width access state system control register 1 syscr1 8 h'fff0 power-down 8 2 system control register 2 syscr2 8 h'fff1 power-down 8 2 interrupt edge select register 1 iegr1 8 h'fff2 interrupts 8 2 interrupt edge select register 2 iegr2 8 h'fff3 interrupts 8 2 interrupt enable register 1 ienr1 8 h'fff4 interrupts 8 2 ? ? ? h'fff5 i/o port ? ? interrupt flag register 1 irr1 8 h'fff6 interrupts 8 2 ? ? ? h'ffe7 i/o port ? ? wake-up interrupt flag register iwpr 8 h'fff8 interrupts 8 2 module standby control register 1 mstcr1 8 h'fff9 power-down 8 2 ? ? ? h'fffa to h'ffff ? ? ? ? eeprom register name abbre- viation bit no address module name data bus width access state eeprom slave address register ? 8 h'ff09 eeprom ? ? eeprom key register ekr 8 h'ff10 eeprom ? ? notes: 1. lvdc: low-voltage det ection circuits (optional) 2. only word access can be used. 3. wdt: watchdog timer
section 20 list of registers rev.5.00 nov. 02, 2005 page 307 of 418 rej09b0028-0500 20.2 register bits the addresses and bit names of the registers in the on-chip peripheral modules are listed below. the 16-bit register is indicated in two rows, 8 bits for each row. register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module name ? ? ? ? ? ? ? ? ? ? lvdcr lvde ? ? ? lvdsel lvdre lvdde lvdue lvdc lvdsr ? ? ? ? ? ? lvddf lvduf (optional) * 1 ? ? ? ? ? ? ? ? ? ? iccr1 ice rcvd mst trs cks3 cks2 cks1 cks0 iic2 iccr2 bbsy scp sdao sdaop scko ? iicrst ? icmr mls wait ? ? bcwp bc2 bc1 bc0 icier tie teie rie nakie stie acke ackbr ackbt icsr tdre tend rdrf nackf stop al/ove aas adz sar sva6 sva5 sva4 sva3 sva2 sva1 sva0 fs icdrt icdrt7 icdrt6 icdrt5 icdrt4 icdrt3 icdrt2 icdrt1 icdrt0 icdrr icdrr7 icdrr6 icdrr5 icdrr4 icdrr3 icdrr2 icdrr1 icdrr0 ? ? ? ? ? ? ? ? ? ? tmrw cts ? bufeb bufea ? pwmd pwmc pwmb timer w tcrw cclr cks2 cks1 cks0 tod toc tob toa tierw ovie ? ? ? imied imiec imieb imiea tsrw ovf ? ? ? imfd imfc imfb imfa tior0 ? iob2 iob1 iob0 ? ioa2 ioa1 ioa0 tior1 ? iod2 iod1 iod0 ? ioc2 ioc1 ioc0 tcnt tcnt15 tcnt14 tcnt13 tcnt12 tcnt11 tcnt10 tcnt9 tcnt8 tcnt7 tcnt6 tcnt5 tcnt4 tcnt3 tcnt2 tcnt1 tcnt0 gra gra15 gra14 gra13 gra12 gra11 gra10 gra9 gra8 gra7 gra6 gra5 gra4 gra3 gra2 gra1 gra0 grb grb15 grb14 grb13 grb12 grb11 grb10 grb9 grb8 grb7 grb6 grb5 grb4 grb3 grb2 grb1 grb0 grc grc15 grc14 grc13 grc12 grc11 grc10 grc9 grc8 grc7 grc6 grc5 grc4 grc3 grc2 grc1 grc0 grd grd15 grd14 grd13 grd12 grd11 grd10 grd9 grd8 grd7 grd6 grd5 grd4 grd3 grd2 grd1 grd0
section 20 list of registers rev.5.00 nov. 02, 2005 page 308 of 418 rej09b0028-0500 register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module name flmcr1 ? swe esu psu ev pv e p rom flmcr2 fler ? ? ? ? ? ? ? flpwcr pdwnd ? ? ? ? ? ? ? ebr1 ? ? ? eb4 eb3 eb2 eb1 eb0 fenr flshe ? ? ? ? ? ? ? tcrv0 cmieb cmiea ovie cclr1 cclr0 cks2 cks1 cks0 timer v tcsrv cmfb cmfa ovf ? os3 os2 os1 os0 tcora tcora7 tcora6 tcora5 tcora4 tcora3 tcora2 tcora1 tcora0 tcorb tcorb7 tcorb6 tcorb5 tcorb4 tcorb3 tcorb2 tcorb1 tcorb0 tcntv tcntv7 tcntv6 tcntv5 tcntv4 tcntv3 tcntv2 tcntv1 tcntv0 tcrv1 ? ? ? tveg1 tveg0 trge ? icks0 tma tma7 tma6 tma5 ? tma3 tma2 tma1 tma0 timer a tca tca7 tca6 tca5 tca4 tca3 tca2 tca1 tca0 smr com chr pe pm stop mp cks1 cks0 sci3 brr brr7 brr6 brr5 brr4 brr3 brr2 brr1 brr0 scr3 tie rie te re mpie teie cke1 cke0 tdr tdr7 tdr6 tdr5 tdr4 tdr3 tdr2 tdr1 tdr0 ssr tdre rdrf oer fer per tend mpbr mpbt rdr rdr7 rdr6 rdr5 rdr4 rdr3 rdr2 rdr1 rdr0 addra ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 ? ? ? ? ? ? a/d converter addrb ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 ? ? ? ? ? ? addrc ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 ? ? ? ? ? ? addrd ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 ? ? ? ? ? ? adcsr adf adie adst scan cks ch2 ch1 ch0 adcr trge ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? tcsrwd b6wi tcwe b4wi tcsrw e b2wi wdon b0wi wrst wdt * 2 tcwd tcwd7 tcwd6 tcwd5 tcwd4 tcwd3 tcwd2 tcwd1 tcwd0
section 20 list of registers rev.5.00 nov. 02, 2005 page 309 of 418 rej09b0028-0500 register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module name tmwd ? ? ? ? cks3 cks2 cks1 cks0 wdt * 2 ? ? ? ? ? ? ? ? ? ? abrkcr rtinte csel1 csel0 acmp2 acmp1 acmp0 dcmp1 dcmp0 address break abrksr abif abie ? ? ? ? ? ? barh barh7 barh6 barh5 barh4 barh3 barh2 barh1 barh0 barl barl7 barl6 barl5 barl4 barl3 barl2 barl1 barl0 bdrh bdrh7 bdrh6 bdrh5 bdrh4 bdrh3 bdrh2 bdrh1 bdrh0 bdrl bdrl7 bdrl6 bdrl5 bdrl4 bdrl3 bdrl2 bdrl1 bdrl0 ? ? ? ? ? ? ? ? ? ? pucr1 pucr17 pucr16 pucr15 pucr14 ? pucr12 pucr11 pucr10 i/o port pucr5 ? ? pucr55 pucr54 pucr53 pucr52 pucr51 pucr50 pdr1 p17 p16 p15 p14 ? p12 p11 p10 pdr2 ? ? ? ? ? p22 p21 p20 pdr5 p57 * 3 p56 * 3 p55 p54 p53 p52 p51 p50 pdr7 ? p76 p75 p74 ? ? ? ? pdr8 p87 p86 p85 p84 p83 p82 p81 p80 pdrb pb7 pb6 pb5 pb4 pb3 pb2 pb1 pb0 pmr1 irq3 irq2 irq1 irq0 ? ? txd tmow pmr5 ? ? wkp5 wkp4 wkp3 wkp2 wkp1 wkp0 pcr1 pcr17 pcr16 pcr15 pcr14 ? pcr12 pcr11 pcr10 pcr2 ? ? ? ? ? pcr22 pcr21 pcr20 pcr5 pcr57 * 3 pcr56 * 3 pcr55 pcr54 pcr53 pcr52 pcr51 pcr50 pcr7 ? pcr76 pcr75 pcr74 ? ? ? ? pcr8 pcr87 pcr86 pcr85 pcr84 pcr83 pcr82 pcr81 pcr80 syscr1 ssby sts2 sts1 sts0 nesel ? ? ? power-down syscr2 smsel lson dton ma2 ma1 ma0 sa1 sa0 iegr1 nmieg ? ? ? ieg3 ie g2 ieg1 ieg0 interrupts iegr2 ? ? wpeg5 wpeg4 wpeg3 wpeg2 wpeg1 wpeg0 ienr1 iendt ienta ienwp ? ien3 ien2 ien1 ien0 irr1 irrdt irrta ? ? irri3 irri2 irri1 irri0 iwpr ? ? iwpf5 iwpf4 iwpf3 iwpf2 iwpf1 iwpf0 mstcr1 ? mstiic msts3 mstad ms twd msttw msttv mstta power-down ? ? ? ? ? ? ? ? ? ?
section 20 list of registers rev.5.00 nov. 02, 2005 page 310 of 418 rej09b0028-0500 ? eeprom register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module name ekr eeprom notes: 1. lvdc: low-voltage det ection circuits (optional) 2. wdt: watchdog timer 3. these bits are reserved in the eeprom stacked f-ztat tm and mask-rom versions.
section 20 list of registers rev.5.00 nov. 02, 2005 page 311 of 418 rej09b0028-0500 20.3 registers states in each operating mode register name reset active sleep subactive subsleep standby module lvdcr initialized ? ? ? ? ? lvdc lvdsr initialized ? ? ? ? ? (optional) * 1 iccr1 initialized ? ? ? ? ? iic2 iccr2 initialized ? ? ? ? ? icmr initialized ? ? ? ? ? icier initialized ? ? ? ? ? icsr initialized ? ? ? ? ? sar initialized ? ? ? ? ? icdrt initialized ? ? ? ? ? icdrr initialized ? ? ? ? ? tmrw initialized ? ? ? ? ? timer w tcrw initialized ? ? ? ? ? tierw initialized ? ? ? ? ? tsrw initialized ? ? ? ? ? tior0 initialized ? ? ? ? ? tior1 initialized ? ? ? ? ? tcnt initialized ? ? ? ? ? gra initialized ? ? ? ? ? grb initialized ? ? ? ? ? grc initialized ? ? ? ? ? grd initialized ? ? ? ? ? flmcr1 initialized ? ? initialized initialized initialized rom flmcr2 initialized ? ? ? ? ? flpwcr initialized ? ? ? ? ? ebr1 initialized ? ? initialized initialized initialized fenr initialized ? ? ? ? ? tcrv0 initialized ? ? initialized initialized initialized timer v tcsrv initialized ? ? initialized initialized initialized tcora initialized ? ? initialized initialized initialized tcorb initialized ? ? initialized initialized initialized
section 20 list of registers rev.5.00 nov. 02, 2005 page 312 of 418 rej09b0028-0500 register name reset active sleep subactive subsleep standby module tcntv initialized ? ? initialized initialized initialized timer v tcrv1 initialized ? ? initialized initialized initialized tma initialized ? ? ? ? ? timer a tca initialized ? ? ? ? ? smr initialized ? ? initialized initialized initialized sci3 brr initialized ? ? initialized initialized initialized scr3 initialized ? ? initialized initialized initialized tdr initialized ? ? initialized initialized initialized ssr initialized ? ? initialized initialized initialized rdr initialized ? ? initialized initialized initialized addra initialized ? ? initialized initialized initialized a/d converter addrb initialized ? ? initialized initialized initialized addrc initialized ? ? initialized initialized initialized addrd initialized ? ? initialized initialized initialized adcsr initialized ? ? initialized initialized initialized adcr initialized ? ? initialized initialized initialized tcsrwd initialized ? ? ? ? ? wdt * 2 tcwd initialized ? ? ? ? ? tmwd initialized ? ? ? ? ? abrkcr initialized ? ? ? ? ? address break abrksr initialized ? ? ? ? ? barh initialized ? ? ? ? ? barl initialized ? ? ? ? ? bdrh initialized ? ? ? ? ? bdrl initialized ? ? ? ? ? pucr1 initialized ? ? ? ? ? i/o port pucr5 initialized ? ? ? ? ? pdr1 initialized ? ? ? ? ? pdr2 initialized ? ? ? ? ? pdr5 initialized ? ? ? ? ? pdr7 initialized ? ? ? ? ? pdr8 initialized ? ? ? ? ? pdrb initialized ? ? ? ? ?
section 20 list of registers rev.5.00 nov. 02, 2005 page 313 of 418 rej09b0028-0500 register name reset active sleep subactive subsleep standby module pmr1 initialized ? ? ? ? ? i/o port pmr5 initialized ? ? ? ? ? pcr1 initialized ? ? ? ? ? pcr2 initialized ? ? ? ? ? pcr5 initialized ? ? ? ? ? pcr7 initialized ? ? ? ? ? pcr8 initialized ? ? ? ? ? syscr1 initialized ? ? ? ? ? power-down syscr2 initialized ? ? ? ? ? power-down iegr1 initialized ? ? ? ? ? interrupts iegr2 initialized ? ? ? ? ? interrupts ienr1 initialized ? ? ? ? ? interrupts irr1 initialized ? ? ? ? ? interrupts iwpr initialized ? ? ? ? ? interrupts mstcr1 initialized ? ? ? ? ? power-down ? eeprom register name reset active sleep subactive subsleep standby module ekr ? ? ? ? ? ? eeprom notes: ? is not initialized 1. lvdc: low-voltage detection circuits (optional) 2. wdt: watchdog timer
section 20 list of registers rev.5.00 nov. 02, 2005 page 314 of 418 rej09b0028-0500
section 21 electric al characteristics rev.5.00 nov. 02, 2005 page 315 of 418 rej09b0028-0500 section 21 electrical characteristics 21.1 absolute maximum ratings table 21.1 absolute maximum ratings item symbol value unit note power supply voltage v cc ?0.3 to +7.0 v * analog power supply voltage av cc ?0.3 to +7.0 v input voltage ports other than ports b and x1 v in ?0.3 to v cc +0.3 v port b ?0.3 to av cc +0.3 v x1 ?0.3 to 4.3 v operating temperature t opr ?20 to +75 c storage temperature t stg ?55 to +125 c note: * permanent damage may result if maximu m ratings are exceeded. normal operation should be under the conditions specified in electrical characteristics. exceeding these values can result in incorrect operation and reduced reliability. 21.2 electrical characteristics (f -ztat? version, eeprom stacked f-ztat tm version) 21.2.1 power supply voltage and operating ranges power supply voltage and os cillation frequency range 10.0 2.0 20.0 3.0 4.0 5.5 v cc (v) osc (mhz) 32.768 3.0 4.0 5.5 v cc (v) w (khz) av cc = 3.3 to 5.5 v active mode sleep mode av cc = 3.3 to 5.5 v all operating modes
section 21 electric al characteristics rev.5.00 nov. 02, 2005 page 316 of 418 rej09b0028-0500 power supply voltage and op erating frequency range 10.0 1.0 20.0 3.0 4.0 5.5 v cc (v) (mhz) 16.384 3.0 4.0 5.5 v cc (v) sub (khz) 8.192 4.096 1250 78.125 2500 3.0 4.0 5.5 v cc (v) (khz) av cc = 3.3 to 5.5 v active mode sleep mode (when ma2 in syscr2 = 0 ) av cc = 3.3 to 5.5 v subactive mode subsleep mode av cc = 3.3 to 5.5 v active mode sleep mode (when ma2 in syscr2 = 1 ) analog power supply voltage and a/d converter accuracy guarantee range 10.0 2.0 20.0 3.3 4.0 5.5 av cc (v) (mhz) v cc = 3.0 to 5.5 v active mode sleep mode
section 21 electric al characteristics rev.5.00 nov. 02, 2005 page 317 of 418 rej09b0028-0500 range of power supply voltage and oscillat ion frequency when low-voltage detection circuit is used operation guarantee range operation guarantee range except a/d conversion accuracy 20.0 16.0 2.0 3.0 4.5 5.5 vcc(v) osc (mhz)
section 21 electric al characteristics rev.5.00 nov. 02, 2005 page 318 of 418 rej09b0028-0500 21.2.2 dc characteristics table 21.2 dc characteristics (1) v cc = 3.0 to 5.5 v, v ss = 0.0 v, t a = ?20 to +75c, unless otherwise indicated. values item symbol applicable pins test condition min typ max unit notes input high voltage v ih res , nmi , wkp0 to wkp5 , irq0 to irq3 , adtrg ,tmriv, v cc = 4.0 to 5.5 v v cc 0.8 ? v cc + 0.3 v tmciv, ftci, ftioa to ftiod, sck3, trgv v cc 0.9 ? v cc + 0.3 rxd, scl, sda, p10 to p12, p14 to p17, p20 to p22, v cc = 4.0 to 5.5 v v cc 0.7 ? v cc + 0.3 v p50 to p57, p74 to p76, p80 to p87 v cc 0.8 ? v cc + 0.3 pb0 to pb7 v cc = 4.0 to 5.5 v v cc 0.7 ? av cc + 0.3 v v cc 0.8 ? av cc + 0.3 osc1 v cc = 4.0 to 5.5 v v cc ? 0.5 ? v cc + 0.3 v v cc ? 0.3 ? v cc + 0.3 input low voltage v il res , nmi , wkp0 to wkp5 , irq0 to irq3 , adtrg ,tmriv, v cc = 4.0 to 5.5 v ?0.3 ? v cc 0.2 v tmciv, ftci, ftioa to ftiod, sck3, trgv ?0.3 ? v cc 0.1 rxd, scl, sda, p10 to p12, p14 to p17, p20 to p22, v cc = 4.0 to 5.5 v ?0.3 ? v cc 0.3 v p50 to p57, p74 to p76, p80 to p87 pb0 to pb7 ?0.3 ? v cc 0.2 osc1 v cc = 4.0 to 5.5 v ?0.3 ? 0.5 v ?0.3 ? 0.3
section 21 electric al characteristics rev.5.00 nov. 02, 2005 page 319 of 418 rej09b0028-0500 values item symbol applicable pins test condition min typ max unit notes output high voltage v oh p10 to p12, p14 to p17, p20 to p22, v cc = 4.0 to 5.5 v ?i oh = 1.5 ma v cc ? 1.0 ? ? v p50 to p55, p74 to p76, p80 to p87 ?i oh = 0.1 ma v cc ? 0.5 ? ? p56, p57 v cc = 4.0 to 5.5 v ?i oh = 0.1 ma v cc ? 2.5 ? ? v v cc = 3.0 to 4.0 v ?i oh = 0.1 ma v cc ? 2.0 ? ? output low voltage v ol p10 to p12, p14 to p17, p20 to p22, v cc = 4.0 to 5.5 vi ol = 1.6 ma ? ? 0.6 v p50 to p57, p74 to p76 i ol = 0.4 ma ? ? 0.4 p80 to p87 v cc = 4.0 to 5.5 v i ol = 20.0 ma ? ? 1.5 v v cc = 4.0 to 5.5 v i ol = 10.0 ma ? ? 1.0 v cc = 4.0 to 5.5 v i ol = 1.6 ma ? ? 0.4 i ol = 0.4 ma ? ? 0.4 scl, sda v cc = 4.0 to 5.5 v i ol = 6.0 ma ? ? 0.6 v i ol = 3.0 ma ? ? 0.4 input/ output leakage current | i il | osc1, nmi , wkp0 to wkp5 , irq0 to irq3 , adtrg , trgv, tmriv, tmciv, ftci, ftioa to ftiod, rxd, sck3, scl, sda v in = 0.5 v to (v cc ? 0.5 v) ? ? 1.0 a p10 to p12, p14 to p17, p20 to p22, p50 to p57, p74 to p76, p80 to p87 v in = 0.5 v to (v cc ? 0.5 v) ? ? 1.0 a pb0 to pb7 v in = 0.5 v to (av cc ? 0.5 v) ? ? 1.0 a
section 21 electric al characteristics rev.5.00 nov. 02, 2005 page 320 of 418 rej09b0028-0500 values item symbol applicable pins test condition min typ max unit notes pull-up mos ?i p p10 to p12, p14 to p17, v cc = 5.0 v, v in = 0.0 v 50.0 ? 300.0 a current p50 to p55 v cc = 3.0 v, v in = 0.0 v ? 60.0 ? reference value all input pins except power supply pins ? ? 15.0 pf input capaci- tance c in sda, scl f = 1 mhz, v in = 0.0 v, t a = 25c ? ? 25.0 pf hd64n3694g active mode current i ope1 v cc active mode 1 v cc = 5.0 v, f osc = 20 mhz ? 20.0 30.0 ma * consump- tion active mode 1 v cc = 3.0 v, f osc = 10 mhz ? 8.0 ? * reference value i ope2 v cc active mode 2 v cc = 5.0 v, f osc = 20 mhz ? 2.0 3.0 ma * active mode 2 v cc = 3.0 v, f osc = 10 mhz ? 1.2 ? * reference value sleep mode current i sleep1 v cc sleep mode 1 v cc = 5.0 v, f osc = 20 mhz ? 16.0 22.5 ma * consump- tion sleep mode 1 v cc = 3.0 v, f osc = 10 mhz ? 8.0 ? * reference value i sleep2 v cc sleep mode 2 v cc = 5.0 v, f osc = 20 mhz ? 1.8 2.7 ma * sleep mode 2 v cc = 3.0 v, f osc = 10 mhz ? 1.2 ? * reference value subactive mode current consump- i sub v cc v cc = 3.0 v 32-khz crystal resonator ( sub = w /2) ? 40.0 70.0 a * tion v cc = 3.0 v 32-khz crystal resonator ( sub = w /8) ? 30.0 ? * reference value
section 21 electric al characteristics rev.5.00 nov. 02, 2005 page 321 of 418 rej09b0028-0500 values item symbol applicable pins test condition min typ max unit notes subsleep mode current consump- tion i subsp v cc v cc = 3.0 v 32-khz crystal resonator ( sub = w /2) ? 30.0 50.0 a * standby mode current consump- tion i stby v cc 32-khz crystal resonator not used ? ? 5.0 a * ram data retaining voltage v ram v cc 2.0 ? ? v note: * pin states during current consumption meas urement are given below (excluding current in the pull-up mos transistors and output buffers). mode res pin internal state other pins oscillator pins active mode 1 v cc operates v cc main clock: ceramic or crystal resonator active mode 2 operates ( osc/64) subclock: pin x 1 = v ss sleep mode 1 v cc only timers operate v cc sleep mode 2 only timers operate ( osc/64) subactive mode v cc operates v cc main clock: ceramic or crystal resonator subsleep mode v cc only timers operate v cc subclock: crystal resonator standby mode v cc cpu and timers both stop v cc main clock: ceramic or crystal resonator subclock: pin x 1 = v ss
section 21 electric al characteristics rev.5.00 nov. 02, 2005 page 322 of 418 rej09b0028-0500 table 21.2 dc characteristics (2) v cc = 3.0 v to 5.5 v, v ss = 0.0 v, t a = ?20c to +75c, unless otherwise indicated. values item symbol applicable pins test condition min typ max unit notes i eew v cc v cc = 5.0 v, t scl = 2.5 s (when writing) ? ? 2.0 ma * i eer v cc v cc = 5.0 v, t scl = 2.5 s (when reading) ? ? 0.3 ma eeprom current consump- tion i eestby v cc v cc = 5.0 v, t scl = 2.5 s (at standby) ? ? 3.0 a note: * the current consum ption of the eeprom chip is shown. for the current consumption of h8/3694n, ad d the above current values to the current consumption of h8/3694f.
section 21 electric al characteristics rev.5.00 nov. 02, 2005 page 323 of 418 rej09b0028-0500 table 21.2 dc characteristics (3) v cc = 3.0 to 5.5 v, v ss = 0.0 v, t a = ?20 to +75c, unless otherwise indicated. applicable values item symbol pins test condition min typ max unit allowable output low current (per pin) i ol output pins except port 8, scl, and sda v cc = 4.0 to 5.5 v ? ? 2.0 ma port 8 ? ? 20.0 port 8 ? ? 10.0 scl and sda ? ? 6.0 output pins except port 8, scl, and sda ? ? 0.5 allowable output low current (total) i ol output pins except port 8, scl, and sda v cc = 4.0 to 5.5 v ? ? 40.0 ma port 8, scl, and sda ? ? 80.0 output pins except port 8, scl, and sda ? ? 20.0 port 8, scl, and sda ? ? 40.0 allowable output high ? ?i oh ? all output pins v cc = 4.0 to 5.5 v ? ? 2.0 ma current (per pin) ? ? 0.2 allowable output high ? ? i oh ? all output pins v cc = 4.0 to 5.5 v ? ? 30.0 ma current (total) ? ? 8.0
section 21 electric al characteristics rev.5.00 nov. 02, 2005 page 324 of 418 rej09b0028-0500 21.2.3 ac characteristics table 21.3 ac characteristics v cc = 3.0 to 5.5 v, v ss = 0.0 v, t a = ?20 to +75c, unless otherwise indicated. applicable values reference item symbol pins test condition min typ max unit figure system clock oscillation f osc osc1, osc2 v cc = 4.0 to 5.5 v 2.0 ? 20.0 mhz * 1 frequency 2.0 10.0 system clock ( ) t cyc 1 ? 64 t osc * 2 cycle time ? ? 12.8 s subclock oscillation frequency f w x1, x2 ? 32.768 ? khz watch clock ( w ) cycle time t w x1, x2 ? 30.5 ? s subclock ( sub ) cycle time t subcyc 2 ? 8 t w * 2 instruction cycle time 2 ? ? t cyc t subcyc oscillation stabilization time (crystal resonator) t rc osc1, osc2 ? ? 10.0 ms oscillation stabilization time (ceramic resonator) t rc osc1, osc2 ? ? 5.0 ms oscillation stabilization time t rcx x1, x2 ? ? 2.0 s external clock t cph osc1 v cc = 4.0 to 5.5 v 20.0 ? ? ns figure 21.1 high width 40.0 ? ? external clock t cpl osc1 v cc = 4.0 to 5.5 v 20.0 ? ? ns low width 40.0 ? ? external clock t cpr osc1 v cc = 4.0 to 5.5 v ? ? 10.0 ns rise time ? ? 15.0 external clock t cpf osc1 v cc = 4.0 to 5.5 v ? ? 10.0 ns fall time ? ? 15.0 res pin low width t rel res at power-on and in modes other than those below t rc ? ? ms figure 21.2 in active mode and sleep mode operation 200 ? ? ns
section 21 electric al characteristics rev.5.00 nov. 02, 2005 page 325 of 418 rej09b0028-0500 applicable values reference item symbol pins test condition min typ max unit figure input pin high width t ih nmi , irq0 to irq3 , wkp0 to wkp5 , tmciv, tmriv, trgv, adtrg , ftci, ftioa to ftiod 2 ? ? t cyc t subcyc figure 21.3 input pin low width t il nmi , irq0 to irq3 , wkp0 to wkp5 , tmciv, tmriv, trgv, adtrg , ftci, ftioa to ftiod 2 ? ? t cyc t subcyc notes: 1. when an external clock is input, the minimum system clock oscillation frequency is 1.0 mhz. 2. determined by ma2, ma1, ma0, sa1, and sa0 of system control register 2 (syscr2).
section 21 electric al characteristics rev.5.00 nov. 02, 2005 page 326 of 418 rej09b0028-0500 table 21.4 i 2 c bus interface timing v cc = 3.0 to 5.5 v, v ss = 0.0 v, t a = ?20 to +75c, unless otherwise indicated. test values reference item symbol condition min typ max unit figure scl input cycle time t scl 12t cyc + 600 ? ? ns figure 21.4 scl input high width t sclh 3t cyc + 300 ? ? ns scl input low width t scll 5t cyc + 300 ? ? ns scl and sda input fall time t sf ? ? 300 ns scl and sda input spike pulse removal time t sp ? ? 1t cyc ns sda input bus-free time t buf 5t cyc ? ? ns start condition input hold time t stah 3t cyc ? ? ns retransmission start condition input setup time t stas 3t cyc ? ? ns setup time for stop condition input t stos 3t cyc ? ? ns data-input setup time t sdas 1t cyc +20 ? ? ns data-input hold time t sdah 0 ? ? ns capacitive load of scl and sda c b 0 ? 400 pf scl and sda output fall time t sf v cc = 4.0 to 5.5 v ? ? 250 ns ? ? 300
section 21 electric al characteristics rev.5.00 nov. 02, 2005 page 327 of 418 rej09b0028-0500 table 21.5 serial communicati on interface (sci) timing v cc = 3.0 to 5.5 v, v ss = 0.0 v, t a = ?20 to +75c, unless otherwise indicated. applicable values reference item symbol pins test condition min typ max unit figure input clock asynchro- nous t scyc sck3 4 ? ? t cyc figure 21.5 cycle clocked synchro- nous 6 ? ? input clock pulse width t sckw sck3 0.4 ? 0.6 t scyc transmit data delay t txd txd v cc = 4.0 v to 5.5 v ? ? 1 t cyc figure 21.6 time (clocked synchronous) ? ? 1 receive data setup t rxs rxd v cc = 4.0 v to 5.5 v 50.0 ? ? ns time (clocked synchronous) 100.0 ? ? receive data hold t rxh rxd v cc = 4.0 v to 5.5 v 50.0 ? ? ns time (clocked synchronous) 100.0 ? ?
section 21 electric al characteristics rev.5.00 nov. 02, 2005 page 328 of 418 rej09b0028-0500 21.2.4 a/d converter characteristics table 21.6 a/d convert er characteristics v cc = 3.0 to 5.5 v, v ss = 0.0 v, t a = ?20 to +75c, unless otherwise indicated. applicable test values reference item symbol pins condition min typ max unit figure analog power supply voltage av cc av cc 3.3 v cc 5.5 v * 1 analog input voltage av in an0 to an7 v ss ? 0.3 ? av cc + 0.3 v analog power supply current ai ope av cc av cc = 5.0 v f osc = 20 mhz ? ? 2.0 ma ai stop1 av cc ? 50 ? a * 2 reference value ai stop2 av cc ? ? 5.0 a * 3 analog input capacitance c ain an0 to an7 ? ? 30.0 pf allowable signal source impedance r ain an0 to an7 ? ? 5.0 k ? resolution (data length) 10 10 10 bit conversion time (single mode) av cc = 3.3 to 5.5 v 134 ? ? t cyc nonlinearity error ? ? 7.5 lsb offset error ? ? 7.5 lsb full-scale error ? ? 7.5 lsb quantization error ? ? 0.5 lsb absolute accuracy ? ? 8.0 lsb conversion time (single mode) av cc = 4.0 to 5.5 v 70 ? ? t cyc nonlinearity error ? ? 7.5 lsb offset error ? ? 7.5 lsb full-scale error ? ? 7.5 lsb quantization error ? ? 0.5 lsb absolute accuracy ? ? 8.0 lsb
section 21 electric al characteristics rev.5.00 nov. 02, 2005 page 329 of 418 rej09b0028-0500 applicable test values reference item symbol pins condition min typ max unit figure conversion time (single mode) av cc = 4.0 to 5.5 v 134 ? ? t cyc nonlinearity error ? ? 3.5 lsb offset error ? ? 3.5 lsb full-scale error ? ? 3.5 lsb quantization error ? ? 0.5 lsb absolute accuracy ? ? 4.0 lsb notes: 1. set av cc = v cc when the a/d converter is not used. 2. ai stop1 is the current in active and sleep m odes while the a/d converter is idle. 3. ai stop2 is the current at reset and in standby, subactive, and subsleep modes while the a/d converter is idle. 21.2.5 watchdog timer characteristics table 21.7 watchdog ti mer characteristics v cc = 3.0 to 5.5 v, v ss = 0.0 v, t a = ?20 to +75c, unless otherwise indicated. applicable test values reference item symbol pins conditi on min typ max unit figure on-chip oscillator overflow time t ovf 0.2 0.4 ? s * note: * shows the time to count from 0 to 255, at which point an internal reset is generated, when the internal oscillator is selected.
section 21 electric al characteristics rev.5.00 nov. 02, 2005 page 330 of 418 rej09b0028-0500 21.2.6 flash memory characteristics table 21.8 flash memory characteristics v cc = 3.0 to 5.5 v, v ss = 0.0 v, t a = ?20 to +75c, unless otherwise indicated. test values item symbol condition min typ max unit programming time (per 128 bytes) * 1 * 2 * 4 t p ? 7 200 ms erase time (per block) * 1 * 3 * 6 t e ? 100 1200 ms reprogramming count n wec 1000 10000 ? times programming wait time after swe bit setting * 1 x 1 ? ? s wait time after psu bit setting * 1 y 50 ? ? s wait time after p bit setting z1 1 n 6 28 30 32 s * 1 * 4 z2 7 n 1000 198 200 202 s z3 additional- programming 8 10 12 s wait time after p bit clear * 1 5 ? ? s wait time after psu bit clear * 1 5 ? ? s wait time after pv bit setting * 1 4 ? ? s wait time after dummy write * 1 2 ? ? s wait time after pv bit clear * 1 2 ? ? s wait time after swe bit clear * 1 100 ? ? s maximum programming count * 1 * 4 * 5 n ? ? 1000 times
section 21 electric al characteristics rev.5.00 nov. 02, 2005 page 331 of 418 rej09b0028-0500 test values item symbol condition min typ max unit erasing wait time after swe bit setting * 1 x 1 ? ? s wait time after esu bit setting * 1 y 100 ? ? s wait time after e bit setting * 1 * 6 z 10 ? 100 ms wait time after e bit clear * 1 10 ? ? s wait time after esu bit clear * 1 10 ? ? s wait time after ev bit setting * 1 20 ? ? s wait time after dummy write * 1 2 ? ? s wait time after ev bit clear * 1 4 ? ? s wait time after swe bit clear * 1 100 ? ? s maximum erase count * 1 * 6 * 7 n ? ? 120 times notes: 1. make the time se ttings in accordance with the program/erase algorithms. 2. the programming time for 128 bytes. (indicate s the total time for which the p bit in flash memory control register 1 (flmcr1) is set. the program-verify time is not included.) 3. the time required to erase one block. (i ndicates the time for which the e bit in flash memory control register 1 (flmcr1) is set. the erase-verify time is not included.) 4. programming time maximum value (t p (max.)) = wait time after p bit setting (z) maximum programming count (n) 5. set the maximum programming count (n) acco rding to the actual se t values of z1, z2, and z3, so that it does not exceed the programming time maximum value (t p (max.)). the wait time after p bit setting (z1, z2) s hould be changed as follows according to the value of the programming count (n). programming count (n) 1 n 6 z1 = 30 s 7 n 1000 z2 = 200 s 6. erase time maximum value (t e (max.)) = wait time after e bit setting (z) maximum erase count (n) 7. set the maximum erase count (n) according to the actual set value of (z), so that it does not exceed the erase time maximum value (t e (max.)).
section 21 electric al characteristics rev.5.00 nov. 02, 2005 page 332 of 418 rej09b0028-0500 21.2.7 eeprom characteristics table 21.9 eeprom characteristics v cc = 3.0 v to 5.5 v, v ss = 0.0 v, t a = ?20c to +75c, unless otherwise specified. test values reference item symbol condition min typ max unit figure scl input cycle time t scl 2500 ? ns figure 21.7 scl input high pulse width t sclh 600 ? ? s scl input low pulse width t scll 1200 ? ? ns scl, sda input spike pulse removal time t sp ? ? 50 ns sda input bus-free time t buf 1200 ? ? ns start condition input hold time t stah 600 ? ? ns retransmit start condition input setup time t stas 600 ? ? ns stop condition input setup time t stos 600 ? ? ns data input setup time t sdas 160 ? ? ns data input hold time t sdah 0 ? ? ns scl, sda input fall time t sf ? ? 300 ns sda input rise time t sr ? ? 300 ns data output hold time t dh 50 ? ? ns scl, sda capacitive load c b 0 ? 400 pf access time t aa 100 ? 900 ns cycle time at writing * t wc ? ? 10 ms reset release time t res ? ? 13 ms note: * cycle time at writing is a time from t he stop condition to write completion (internal control).
section 21 electric al characteristics rev.5.00 nov. 02, 2005 page 333 of 418 rej09b0028-0500 21.2.8 power-supply-voltage detection circuit characteristics (optional) table 21.10 power-supply-voltage de tection circuit characteristics v ss = 0.0 v, t a = ?20 to +75c, unless otherwise indicated. values item symbol test condition min typ max unit power-supply falling detection voltage vint (d) lvdsel = 0 3.3 3.7 ? v power-supply rising detection voltage vint (u) lvdsel = 0 ? 4.0 4.5 v reset detection voltage 1 * 1 vreset1 lvdsel = 0 ? 2.3 2.7 v reset detection voltage 2 * 2 vreset2 lvdsel = 1 3.0 3.6 4.2 v lower-limit voltage of lvdr operation * 3 v lvdrmin 1.0 ? ? v lvd stabilization time t lvdon 50 ? ? s current consumption in standby mode i stby lvde = 1, vcc = 5.0 v, when a 32- khz crystal resonator is not used ? ? 350 a notes: 1. this voltage should be used when t he falling and rising voltage detection function is used. 2. select the low-voltage reset 2 when on ly the low-voltage detection reset is used. 3. when the power-supply voltage (vcc) falls below v lvdrmin = 1.0 v and then rises, a reset may not occur. therefore suffi cient evaluation is required.
section 21 electric al characteristics rev.5.00 nov. 02, 2005 page 334 of 418 rej09b0028-0500 21.2.9 power-on reset circuit characteristics (optional) table 21.11 power-on rese t circuit characteristics v ss = 0.0 v, t a = ?20 to +75c, unless otherwise indicated. values item symbol test condition min typ max unit pull-up resistance of res pin r res 100 150 ? k ? power-on reset start voltage * v por ? ? 100 mv note: * the power-supply voltage (vcc) must fall below vpor = 100 mv and then rise after charge of the res pin is removed completely. in order to remove charge of the res pin, it is recommended that the diode be placed in the vcc side. if the power-supply voltage (vcc) rises from the point over 100 mv, a power-on reset may not occur. 21.3 electrical characteristics (mask-rom version, eeprom stacked mask-rom version) 21.3.1 power supply voltage and operating ranges power supply voltage and os cillation frequency range 10.0 2.0 20.0 2.7 4.0 5.5 v cc (v) osc (mhz) 32.768 2.7 4.0 5.5 v cc (v) w (khz) av cc = 3.0 to 5.5 v active mode sleep mode av cc = 3.0 to 5.5 v all operating modes
section 21 electric al characteristics rev.5.00 nov. 02, 2005 page 335 of 418 rej09b0028-0500 power supply voltage and op erating frequency range 10.0 1.0 20.0 2.7 4.0 5.5 v cc (v) (mhz) 16.384 2.7 4.0 5.5 v cc (v) sub (khz) 8.192 4.096 1250 78.125 2500 2.7 4.0 5.5 v cc (v) (khz) av cc = 3.0 to 5.5 v active mode sleep mode (when ma2 in syscr2 = 0) av cc = 3.0 to 5.5 v subactive mode subsleep mode av cc = 3.0 to 5.5 v active mode sleep mode (when ma2 in syscr2 = 1)
section 21 electric al characteristics rev.5.00 nov. 02, 2005 page 336 of 418 rej09b0028-0500 analog power supply voltage and a/d converter accuracy guarantee range 10.0 2.0 20.0 3.0 4.0 5.5 av cc (v) (mhz) v cc = 2.7 to 5.5 v active mode sleep mode range of power supply voltage and oscillat ion frequency when low-voltage detection circuit is used operation guarantee range operation guarantee range except a/d conversion accuracy 20.0 16.0 2.0 3.0 4.5 5.5 vcc(v) osc (mhz)
section 21 electric al characteristics rev.5.00 nov. 02, 2005 page 337 of 418 rej09b0028-0500 21.3.2 dc characteristics table 21.12 dc characteristics (1) v cc = 2.7 to 5.5 v, v ss = 0.0 v, t a = ?20 to +75c, unless otherwise indicated. values item symbol applicable pins test condition min typ max unit notes input high voltage v ih res , nmi , wkp0 to wkp5 , irq0 to irq3 , adtrg ,tmriv, v cc = 4.0 to 5.5 v v cc 0.8 ? v cc + 0.3 v tmciv, ftci, ftioa to ftiod, sck3, trgv v cc 0.9 ? v cc + 0.3 rxd, scl, sda, p10 to p12, p14 to p17, p20 to p22, v cc = 4.0 to 5.5 v v cc 0.7 ? v cc + 0.3 v p50 to p57, p74 to p76, p80 to p87 v cc 0.8 ? v cc + 0.3 pb0 to pb7 v cc = 4.0 to 5.5 v v cc 0.7 ? av cc + 0.3 v v cc 0.8 ? av cc + 0.3 osc1 v cc = 4.0 to 5.5 v v cc ? 0.5 ? v cc + 0.3 v v cc ? 0.3 ? v cc + 0.3 input low voltage v il res , nmi , wkp0 to wkp5 , irq0 to irq3 , adtrg ,tmriv, v cc = 4.0 to 5.5 v ?0.3 ? v cc 0.2 v tmciv, ftci, ftioa to ftiod, sck3, trgv ?0.3 ? v cc 0.1 rxd, scl, sda, p10 to p12, p14 to p17, p20 to p22, v cc = 4.0 to 5.5 v ?0.3 ? v cc 0.3 v p50 to p57, p74 to p76, p80 to p87, pb0 to pb7 ?0.3 ? v cc 0.2 osc1 v cc = 4.0 to 5.5 v ?0.3 ? 0.5 v ?0.3 ? 0.3
section 21 electric al characteristics rev.5.00 nov. 02, 2005 page 338 of 418 rej09b0028-0500 values item symbol applicable pins test condition min typ max unit notes output high voltage v oh p10 to p12, p14 to p17, p20 to p22, v cc = 4.0 to 5.5 v ?i oh = 1.5 ma v cc ? 1.0 ? ? v p50 to p55, p74 to p76, p80 to p87 ?i oh = 0.1 ma v cc ? 0.5 ? ? p56, p57 v cc = 4.0 to 5.5 v ?i oh = 0.1 ma v cc ? 2.5 ? ? v v cc =2.7 to 4.0 v ?i oh = 0.1 ma v cc ? 2.0 ? ? output low voltage v ol p10 to p12, p14 to p17, p20 to p22, v cc = 4.0 to 5.5 v i ol = 1.6 ma ? ? 0.6 v p50 to p57, p74 to p76 i ol = 0.4 ma ? ? 0.4 p80 to p87 v cc = 4.0 to 5.5 v i ol = 20.0 ma ? ? 1.5 v v cc = 4.0 to 5.5 v i ol = 10.0 ma ? ? 1.0 v cc = 4.0 to 5.5 v i ol = 1.6 ma ? ? 0.4 i ol = 0.4 ma ? ? 0.4 scl, sda v cc = 4.0 to 5.5 v i ol = 6.0 ma ? ? 0.6 v i ol = 3.0 ma ? ? 0.4 input/ output leakage current | i il | osc1, nmi , wkp0 to wkp5 , irq0 to irq3 , adtrg , trgv, tmriv, tmciv, ftci, ftioa to ftiod, rxd, sck3, scl, sda v in = 0.5 v to (v cc ? 0.5 v) ? ? 1.0 a p10 to p12, p14 to p17, p20 to p22, p50 to p57, p74 to p76, p80 to p87 v in = 0.5 v to (v cc ? 0.5 v) ? ? 1.0 a pb0 to pb7 v in = 0.5 v to (av cc ? 0.5 v) ? ? 1.0 a
section 21 electric al characteristics rev.5.00 nov. 02, 2005 page 339 of 418 rej09b0028-0500 values item symbol applicable pins test condition min typ max unit notes pull-up mos ?i p p10 to p12, p14 to p17, v cc = 5.0 v, v in = 0.0 v 50.0 ? 300.0 a current p50 to p55 v cc = 3.0 v, v in = 0.0 v ? 60.0 ? reference value all input pins except power supply pins ? ? 15.0 pf input capaci- tance c in sda, scl f = 1 mhz, v in = 0.0 v, t a = 25c ? ? 25.0 pf HD6483694G active mode current i ope1 v cc active mode 1 v cc = 5.0 v, f osc = 20 mhz ? 20.0 30.0 ma * consump- tion active mode 1 v cc = 3.0 v, f osc = 10 mhz ? 8.0 ? * reference value i ope2 v cc active mode 2 v cc = 5.0 v, f osc = 20 mhz ? 2.0 3.0 ma * active mode 2 v cc = 3.0 v, f osc = 10 mhz ? 1.2 ? * reference value sleep mode current i sleep1 v cc sleep mode 1 v cc = 5.0 v, f osc = 20 mhz ? 10.0 17.5 ma * consump- tion sleep mode 1 v cc = 3.0 v, f osc = 10 mhz ? 5.5 ? * reference value i sleep2 v cc sleep mode 2 v cc = 5.0 v, f osc = 20 mhz ? 1.6 2.4 ma * sleep mode 2 v cc = 3.0 v, f osc = 10 mhz ? 0.8 ? * reference value subactive mode current consump- i sub v cc v cc = 3.0 v 32-khz crystal resonator ( sub = w /2) ? 40.0 70.0 a * tion v cc = 3.0 v 32-khz crystal resonator ( sub = w /8) ? 30.0 ? * reference value
section 21 electric al characteristics rev.5.00 nov. 02, 2005 page 340 of 418 rej09b0028-0500 values item symbol applicable pins test condition min typ max unit notes subsleep mode current consump- tion i subsp v cc v cc = 3.0 v 32-khz crystal resonator ( sub = w /2) ? 30.0 50.0 a * standby mode current consump- tion i stby v cc 32-khz crystal resonator not used ? ? 5.0 a * ram data retaining voltage v ram v cc 2.0 ? ? v note: * pin states during current consumption meas urement are given below (excluding current in the pull-up mos transistors and output buffers). mode res pin internal state other pins oscillator pins active mode 1 v cc operates v cc main clock: ceramic or crystal resonator active mode 2 operates ( osc/64) subclock: pin x 1 = v ss sleep mode 1 v cc only timers operate v cc sleep mode 2 only timers operate ( osc/64) subactive mode v cc operates v cc main clock: ceramic or crystal resonator subsleep mode v cc only timers operate v cc subclock: crystal resonator standby mode v cc cpu and timers both stop v cc main clock: ceramic or crystal resonator subclock: pin x 1 = v ss
section 21 electric al characteristics rev.5.00 nov. 02, 2005 page 341 of 418 rej09b0028-0500 table 21.12 dc characteristics (2) v cc = 2.7 v to 5.5 v, v ss = 0.0 v, t a = ?20c to +75c, unless otherwise indicated. values item symbol applicable pins test condition min typ max unit notes i eew v cc v cc = 5.0 v, t scl = 2.5 s (when writing) ? ? 2.0 ma * i eer v cc v cc = 5.0 v, t scl = 2.5 s (when reading) ? ? 0.3 ma eeprom current consump- tion i eestby v cc v cc = 5.0 v, t scl = 2.5 s (at standby) ? ? 3.0 a note: * the current consum ption of the eeprom chip is shown. for the current consumption of h8/3694n, ad d the above current values to the current consumption of h8/3694.
section 21 electric al characteristics rev.5.00 nov. 02, 2005 page 342 of 418 rej09b0028-0500 table 21.12 dc characteristics (3) v cc = 2.7 to 5.5 v, v ss = 0.0 v, t a = ?20 to +75c, unless otherwise indicated. applicable values item symbol pins test condition min typ max unit allowable output low current (per pin) i ol output pins except port 8, scl, and sda v cc = 4.0 to 5.5 v ? ? 2.0 ma port 8 ? ? 20.0 port 8 ? ? 10.0 scl, and sda ? ? 6.0 output pins except port 8, scl, and sda ? ? 0.5 allowable output low current (total) i ol output pins except port 8, scl, and sda v cc = 4.0 to 5.5 v ? ? 40.0 ma port 8, scl, and sda ? ? 80.0 output pins except port 8, scl, and sda ? ? 20.0 port 8, scl, and sda ? ? 40.0 allowable output high ? ?i oh ? all output pins v cc = 4.0 to 5.5 v ? ? 2.0 ma current (per pin) ? ? 0.2 allowable output high ? ? i oh ? all output pins v cc = 4.0 to 5.5 v ? ? 30.0 ma current (total) ? ? 8.0
section 21 electric al characteristics rev.5.00 nov. 02, 2005 page 343 of 418 rej09b0028-0500 21.3.3 ac characteristics table 21.13 ac characteristics v cc = 2.7 to 5.5 v, v ss = 0.0 v, t a = ?20 to +75c, unless otherwise indicated. applicable values reference item symbol pins test condition min typ max unit figure system clock oscillation f osc osc1, osc2 v cc = 4.0 to 5.5 v 2.0 ? 20.0 mhz * 1 frequency 2.0 10.0 system clock ( ) t cyc 1 ? 64 t osc * 2 cycle time ? ? 12.8 s subclock oscillation frequency f w x1, x2 ? 32.768 ? khz watch clock ( w ) cycle time t w x1, x2 ? 30.5 ? s subclock ( sub ) cycle time t subcyc 2 ? 8 t w * 2 instruction cycle time 2 ? ? t cyc t subcyc oscillation stabilization time (crystal resonator) t rc osc1, osc2 ? ? 10.0 ms oscillation stabilization time (ceramic resonator) t rc osc1, osc2 ? ? 5.0 ms oscillation stabilization time t rcx x1, x2 ? ? 2.0 s external clock t cph osc1 v cc = 4.0 to 5.5 v 20.0 ? ? ns figure 21.1 high width 40.0 ? ? external clock t cpl osc1 v cc = 4.0 to 5.5 v 20.0 ? ? ns low width 40.0 ? ? external clock t cpr osc1 v cc = 4.0 to 5.5 v ? ? 10.0 ns rise time ? ? 15.0 external clock t cpf osc1 v cc = 4.0 to 5.5 v ? ? 10.0 ns fall time ? ? 15.0 res pin low width t rel res at power-on and in modes other than those below t rc ? ? ms figure 21.2 in active mode and sleep mode operation 200 ? ? ns
section 21 electric al characteristics rev.5.00 nov. 02, 2005 page 344 of 418 rej09b0028-0500 applicable values reference item symbol pins test condition min typ max unit figure input pin high width t ih nmi , irq0 to irq3 , wkp0 to wkp5 , tmciv, tmriv, trgv, adtrg , ftci, ftioa to ftiod 2 ? ? t cyc t subcyc figure 21.3 input pin low width t il nmi , irq0 to irq3 , wkp0 to wkp5 , tmciv, tmriv, trgv, adtrg , ftci, ftioa to ftiod 2 ? ? t cyc t subcyc notes: 1 when an external clock is input, the minimum system clock oscillation frequency is 1.0 mhz. 2. determined by ma2, ma1, ma0, sa1, and sa0 of system control register 2 (syscr2).
section 21 electric al characteristics rev.5.00 nov. 02, 2005 page 345 of 418 rej09b0028-0500 table 21.14 i 2 c bus interface timing v cc = 2.7 v to 5.5 v, v ss = 0.0 v, t a = ?20 to +75c, unless otherwise specified. test values reference item symbol condition min typ max unit figure scl input cycle time t scl 12t cyc + 600 ? ? ns figure 21.4 scl input high width t sclh 3t cyc + 300 ? ? ns scl input low width t scll 5t cyc + 300 ? ? ns scl and sda input fall time t sf ? ? 300 ns scl and sda input spike pulse removal time t sp ? ? 1t cyc ns sda input bus-free time t buf 5t cyc ? ? ns start condition input hold time t stah 3t cyc ? ? ns retransmission start condition input setup time t stas 3t cyc ? ? ns setup time for stop condition input t stos 3t cyc ? ? ns data-input setup time t sdas 1t cyc +20 ? ? ns data-input hold time t sdah 0 ? ? ns capacitive load of scl and sda c b 0 ? 400 pf scl and sda output fall time t sf v cc = 4.0 to 5.5 v ? ? 250 ns ? ? 300
section 21 electric al characteristics rev.5.00 nov. 02, 2005 page 346 of 418 rej09b0028-0500 table 21.15 serial communicati on interface (sci) timing v cc = 2.7 v to 5.5 v, v ss = 0.0 v, t a = ?20 to +75c, unless otherwise specified. applicable values reference item symbol pins test condition min typ max unit figure input clock asynchro- nous t scyc sck3 4 ? ? t cyc figure 21.5 cycle clocked synchronous 6 ? ? input clock pulse width t sckw sck3 0.4 ? 0.6 t scyc transmit data delay t txd txd v cc = 4.0 to 5.5 v ? ? 1 t cyc figure 21.6 time (clocked synchronous) ? ? 1 receive data setup t rxs rxd v cc = 4.0 to 5.5 v 50.0 ? ? ns time (clocked synchronous) 100.0 ? ? receive data hold t rxh rxd v cc = 4.0 to 5.5 v 50.0 ? ? ns time (clocked synchronous) 100.0 ? ?
section 21 electric al characteristics rev.5.00 nov. 02, 2005 page 347 of 418 rej09b0028-0500 21.3.4 a/d converter characteristics table 21.16 a/d converter characteristics v cc = 2.7 to 5.5 v, v ss = 0.0 v, t a = ?20 to +75c, unless otherwise indicated. applicable test values reference item symbol pins condition min typ max unit figure analog power supply voltage av cc av cc 3.0 v cc 5.5 v * 1 analog input voltage av in an0 to an7 v ss ? 0.3 ? av cc + 0.3 v analog power supply current ai ope av cc av cc = 5.0 v f osc = 20 mhz ? ? 2.0 ma ai stop1 av cc ? 50 ? a * 2 reference value ai stop2 av cc ? ? 5.0 a * 3 analog input capacitance c ain an0 to an7 ? ? 30.0 pf allowable signal source impedance r ain an0 to an7 ? ? 5.0 k ? resolution (data length) 10 10 10 bit conversion time (single mode) av cc = 3.0 to 5.5 v 134 ? ? t cyc nonlinearity error ? ? 7.5 lsb offset error ? ? 7.5 lsb full-scale error ? ? 7.5 lsb quantization error ? ? 0.5 lsb absolute accuracy ? ? 8.0 lsb conversion time (single mode) av cc = 4.0 to 5.5 v 70 ? ? t cyc nonlinearity error ? ? 7.5 lsb offset error ? ? 7.5 lsb full-scale error ? ? 7.5 lsb quantization error ? ? 0.5 lsb absolute accuracy ? ? 8.0 lsb
section 21 electric al characteristics rev.5.00 nov. 02, 2005 page 348 of 418 rej09b0028-0500 applicable test values reference item symbol pins condition min typ max unit figure conversion time (single mode) av cc = 4.0 to 5.5 v 134 ? ? t cyc nonlinearity error ? ? 3.5 lsb offset error ? ? 3.5 lsb full-scale error ? ? 3.5 lsb quantization error ? ? 0.5 lsb absolute accuracy ? ? 4.0 lsb notes: 1 set av cc = v cc when the a/d converter is not used. 2. ai stop1 is the current in active and sleep m odes while the a/d converter is idle. 3. ai stop2 is the current at reset and in standby, subactive, and subsleep modes while the a/d converter is idle. 21.3.5 watchdog timer characteristics table 21.17 watchdog timer characteristics v cc = 2.7 to 5.5 v, v ss = 0.0 v, t a = ?20 to +75c, unless otherwise indicated. applicable test values reference item symbol pins conditi on min typ max unit figure on-chip oscillator overflow time t ovf 0.2 0.4 ? s * note: * shows the time to count from 0 to 255, at which point an internal reset is generated, when the internal oscillator is selected.
section 21 electric al characteristics rev.5.00 nov. 02, 2005 page 349 of 418 rej09b0028-0500 21.3.6 eeprom characteristics table 21.18 eeprom characteristics v cc = 2.7 v to 5.5 v, v ss = 0.0 v, t a = ?20c to +75c, unless otherwise indicated. test values reference item symbol condition min typ max unit figure scl input cycle time t scl 2500 ? ns figure 21.7 scl input high pulse width t sclh 600 ? ? s scl input low pulse width t scll 1200 ? ? ns scl, sda input spike pulse removal time t sp ? ? 50 ns sda input bus-free time t buf 1200 ? ? ns start condition input hold time t stah 600 ? ? ns retransmit start condition input setup time t stas 600 ? ? ns stop condition input setup time t stos 600 ? ? ns data input setup time t sdas 160 ? ? ns data input hold time t sdah 0 ? ? ns scl, sda input fall time t sf ? ? 300 ns sda input rise time t sr ? ? 300 ns data output hold time t dh 50 ? ? ns scl, sda capacitive load c b 0 ? 400 pf access time t aa 100 ? 900 ns cycle time at writing * t wc ? ? 10 ms reset release time t res ? ? 13 ms note: * cycle time at writing is a time from t he stop condition to write completion (internal control).
section 21 electric al characteristics rev.5.00 nov. 02, 2005 page 350 of 418 rej09b0028-0500 21.3.7 power-supply-voltage detection circuit characteristics (optional) table 21.19 power-supply-voltage de tection circuit characteristics v ss = 0.0 v, t a = ?20 to +75c, unless otherwise indicated. values item symbol test condition min typ max unit power-supply falling detection voltage vint (d) lvdsel = 0 3.3 3.7 ? v power-supply rising detection voltage vint (u) lvdsel = 0 ? 4.0 4.5 v reset detection voltage 1 * 1 vreset1 lvdsel = 0 ? 2.3 2.7 v reset detection voltage 2 * 2 vreset2 lvdsel = 1 3.0 3.6 4.2 v lower-limit voltage of lvdr operation * 3 v lvdrmin 1.0 ? ? v lvd stabilization time t lvdon 50 ? ? s current consumption in standby mode i stby lvde = 1, vcc = 5.0 v, when a 32- khz crystal resonator is not used ? ? 350 a notes: 1. this voltage should be used when t he falling and rising voltage detection function is used. 2. select the low-voltage reset 2 when on ly the low-voltage detection reset is used. 3. when the power-supply voltage (vcc) falls below v lvdrmin = 1.0 v and then rises, a reset may not occur. therefore suffi cient evaluation is required.
section 21 electric al characteristics rev.5.00 nov. 02, 2005 page 351 of 418 rej09b0028-0500 21.3.8 power-on reset circuit characteristics (optional) table 21.20 power-on rese t circuit characteristics v ss = 0.0 v, t a = ?20 to +75c, unless otherwise indicated. values item symbol test condition min typ max unit pull-up resistance of res pin r res 100 150 ? k ? power-on reset start voltage * v por ? ? 100 mv note: * the power-supply voltage (vcc) must fall below vpor = 100 mv and then rise after charge of the res pin is removed completely. in order to remove charge of the res pin, it is recommended that the diode be placed in the vcc side. if the power-supply voltage (vcc) rises from the point over 100 mv, a power-on reset may not occur. 21.4 operation timing t osc v ih v il t cph t cpl t cpr osc1 t cpf figure 21.1 system clock input timing
section 21 electric al characteristics rev.5.00 nov. 02, 2005 page 352 of 418 rej09b0028-0500 t rel v il res t rel v il v cc 0.7 v cc osc1 figure 21.2 res low width timing v ih v il t il nmi irq0 to irq3 wkp0 to wkp5 adtrg ftci ftioa to ftiod tmciv, tmriv trgv t ih figure 21.3 input timing scl v ih v il t stah t buf p * s * t sf t scl t sdah t sclh t scll sda sr * t stas t sp t stos t sdas p * note: * s, p, and sr represent the following: s: start condition p: stop condition sr: retransmission start condition figure 21.4 i 2 c bus interface input/output timing
section 21 electric al characteristics rev.5.00 nov. 02, 2005 page 353 of 418 rej09b0028-0500 t scyc t sckw sck3 figure 21.5 sck3 input clock timing t scyc t txd t rxs t rxh v oh v or v ih oh v or v il ol * * * v ol * sck3 txd (transmit data) rxd (receive data) note: * output timing reference levels output high: output low: load conditions are shown in figure 21.8. v = 2.0 v v = 0.8 v oh ol figure 21.6 sci input/output ti ming in clocked synchronous mode
section 21 electric al characteristics rev.5.00 nov. 02, 2005 page 354 of 418 rej09b0028-0500 scl sda (in) sda (out) t sf t sp t sr t stas t sdah t stos t sclh t scll 1/f scl t buf t sdas t stah t aa t dh figure 21.7 eeprom bus timing 21.5 output load condition v cc 2.4 k ? 12 k ? 30 pf lsi output pin figure 21.8 output load circuit
appendix rev.5.00 nov. 02, 2005 page 355 of 418 rej09b0028-0500 appendix a instruction set a.1 instruction list condition code symbol description rd general destination register rs general source register rn general register erd general destination register (address register or 32-bit register) ers general source register (addr ess register or 32-bit register) ern general register (32-bit register) (ead) destination operand (eas) source operand pc program counter sp stack pointer ccr condition-code register n n (negative) flag in ccr z z (zero) flag in ccr v v (overflow) flag in ccr c c (carry) flag in ccr disp displacement transfer from the operand on the left to the operand on the right, or transition from the state on the left to the state on the right + addition of the operands on both sides ? subtraction of the op erand on the right from the operand on the left multiplication of the operands on both sides division of the operand on the left by the operand on the right logical and of the operands on both sides logical or of the operands on both sides logical exclusive or of the operands on both sides ? not (logical complement) ( ), < > contents of operand note: general registers include 8-bit registers (r0h to r7h and r0l to r7l) and 16-bit registers (r0 to r7 and e0 to e7).
appendix rev.5.00 nov. 02, 2005 page 356 of 418 rej09b0028-0500 condition code notation (cont) symbol description ? changed according to execution result * undetermined (no guaranteed value) 0 cleared to 0 1 set to 1 ? not affected by execution of the instruction ? varies depending on conditions, described in notes
appendix rev.5.00 nov. 02, 2005 page 357 of 418 rej09b0028-0500 table a.1 instruction set 1. data transfer instructions mnemonic operand size addressing mode and instruction length (bytes) no. of states * 1 condition code ihnzvc #xx rn @ern @(d, ern) @?ern/@ern+ @aa @(d, pc) @@aa ? mov.b #xx:8, rd mov.b rs, rd mov.b @ers, rd mov.b @(d:16, ers), rd mov.b @(d:24, ers), rd mov.b @ers+, rd mov.b @aa:8, rd mov.b @aa:16, rd mov.b @aa:24, rd mov.b rs, @erd mov.b rs, @(d:16, erd) mov.b rs, @(d:24, erd) mov.b rs, @?erd mov.b rs, @aa:8 mov.b rs, @aa:16 mov.b rs, @aa:24 mov.w #xx:16, rd mov.w rs, rd mov.w @ers, rd mov.w @(d:16, ers), rd mov.w @(d:24, ers), rd mov.w @ers+, rd mov.w @aa:16, rd mov.w @aa:24, rd mov.w rs, @erd mov.w rs, @(d:16, erd) mov.w rs, @(d:24, erd) operation #xx:8 rd8 rs8 rd8 @ers rd8 @(d:16, ers) rd8 @(d:24, ers) rd8 @ers rd8 ers32+1 ers32 @aa:8 rd8 @aa:16 rd8 @aa:24 rd8 rs8 @erd rs8 @(d:16, erd) rs8 @(d:24, erd) erd32?1 erd32 rs8 @erd rs8 @aa:8 rs8 @aa:16 rs8 @aa:24 #xx:16 rd16 rs16 rd16 @ers rd16 @(d:16, ers) rd16 @(d:24, ers) rd16 @ers rd16 ers32+2 @erd32 @aa:16 rd16 @aa:24 rd16 rs16 @erd rs16 @(d:16, erd) rs16 @(d:24, erd) b b b b b b b b b b b b b b b b w w w w w w w w w w w 2 4 2 2 2 2 2 2 4 8 4 8 4 8 4 8 2 2 2 2 4 6 2 4 6 4 6 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 2 4 6 10 6 4 6 8 4 6 10 6 4 6 8 4 2 4 6 10 6 6 8 4 6 10 normal advanced ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? mov
appendix rev.5.00 nov. 02, 2005 page 358 of 418 rej09b0028-0500 mnemonic operand size addressing mode and instruction length (bytes) no. of states * 1 condition code ihnzvc #xx rn @ern @(d, ern) @?ern/@ern+ @aa @(d, pc) @@aa ? mov.w rs, @?erd mov.w rs, @aa:16 mov.w rs, @aa:24 mov.l #xx:32, rd mov.l ers, erd mov.l @ers, erd mov.l @(d:16, ers), erd mov.l @(d:24, ers), erd mov.l @ers+, erd mov.l @aa:16, erd mov.l @aa:24, erd mov.l ers, @erd mov.l ers, @(d:16, erd) mov.l ers, @(d:24, erd) mov.l ers, @?erd mov.l ers, @aa:16 mov.l ers, @aa:24 pop.w rn pop.l ern push.w rn push.l ern movfpe @aa:16, rd movtpe rs, @aa:16 operation erd32?2 erd32 rs16 @erd rs16 @aa:16 rs16 @aa:24 #xx:32 rd32 ers32 erd32 @ers erd32 @(d:16, ers) erd32 @(d:24, ers) erd32 @ers erd32 ers32+4 ers32 @aa:16 erd32 @aa:24 erd32 ers32 @erd ers32 @(d:16, erd) ers32 @(d:24, erd) erd32?4 erd32 ers32 @erd ers32 @aa:16 ers32 @aa:24 @sp rn16 sp+2 sp @sp ern32 sp+4 sp sp?2 sp rn16 @sp sp?4 sp ern32 @sp cannot be used in this lsi cannot be used in this lsi w w w l l l l l l l l l l l l l l w l w l b b 6 2 4 4 6 10 6 10 2 4 4 4 6 6 8 6 8 4 4 2 4 2 4 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6 6 8 6 2 8 10 14 10 10 12 8 10 14 10 10 12 6 10 6 10 normal advanced ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? cannot be used in this lsi cannot be used in this lsi mov pop push movfpe movtpe
appendix rev.5.00 nov. 02, 2005 page 359 of 418 rej09b0028-0500 2. arithmetic instructions mnemonic operand size addressing mode and instruction length (bytes) no. of states * 1 condition code ihnzvc #xx rn @ern @(d, ern) @?ern/@ern+ @aa @(d, pc) @@aa ? add.b #xx:8, rd add.b rs, rd add.w #xx:16, rd add.w rs, rd add.l #xx:32, erd add.l ers, erd addx.b #xx:8, rd addx.b rs, rd adds.l #1, erd adds.l #2, erd adds.l #4, erd inc.b rd inc.w #1, rd inc.w #2, rd inc.l #1, erd inc.l #2, erd daa rd sub.b rs, rd sub.w #xx:16, rd sub.w rs, rd sub.l #xx:32, erd sub.l ers, erd subx.b #xx:8, rd subx.b rs, rd subs.l #1, erd subs.l #2, erd subs.l #4, erd dec.b rd dec.w #1, rd dec.w #2, rd operation rd8+#xx:8 rd8 rd8+rs8 rd8 rd16+#xx:16 rd16 rd16+rs16 rd16 erd32+#xx:32 erd32 erd32+ers32 erd32 rd8+#xx:8 +c rd8 rd8+rs8 +c rd8 erd32+1 erd32 erd32+2 erd32 erd32+4 erd32 rd8+1 rd8 rd16+1 rd16 rd16+2 rd16 erd32+1 erd32 erd32+2 erd32 rd8 decimal adjust rd8 rd8?rs8 rd8 rd16?#xx:16 rd16 rd16?rs16 rd16 erd32?#xx:32 erd32 erd32?ers32 erd32 rd8?#xx:8?c rd8 rd8?rs8?c rd8 erd32?1 erd32 erd32?2 erd32 erd32?4 erd32 rd8?1 rd8 rd16?1 rd16 rd16?2 rd16 b b w w l l b b l l l b w w l l b b w w l l b b l l l b w w 2 4 6 2 4 6 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? (1) (1) (2) (2) ? ? ? ? ? ? ? ? * (1) (1) (2) (2) ? ? ? ? ? ? 2 2 4 2 6 2 2 2 2 2 2 2 2 2 2 2 2 2 4 2 6 2 2 2 2 2 2 2 2 2 normal advanced ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? (3) (3) ? ? ? (3) (3) ? ? ? ? ? ? ? ? ?? ? ? ? ? ? ? ? ? ? ? ? ? ? ? * ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? add addx adds inc daa sub subx subs dec
appendix rev.5.00 nov. 02, 2005 page 360 of 418 rej09b0028-0500 mnemonic operand size addressing mode and instruction length (bytes) no. of states * 1 condition code ihnzvc #xx rn @ern @(d, ern) @?ern/@ern+ @aa @(d, pc) @@aa ? dec.l #1, erd dec.l #2, erd das.rd mulxu. b rs, rd mulxu. w rs, erd mulxs. b rs, rd mulxs. w rs, erd divxu. b rs, rd divxu. w rs, erd divxs. b rs, rd divxs. w rs, erd cmp.b #xx:8, rd cmp.b rs, rd cmp.w #xx:16, rd cmp.w rs, rd cmp.l #xx:32, erd cmp.l ers, erd operation erd32?1 erd32 erd32?2 erd32 rd8 decimal adjust rd8 rd8 rs8 rd16 (unsigned multiplication) rd16 rs16 erd32 (unsigned multiplication) rd8 rs8 rd16 (signed multiplication) rd16 rs16 erd32 (signed multiplication) rd16 rs8 rd16 (rdh: remainder, rdl: quotient) (unsigned division) erd32 rs16 erd32 (ed: remainder, rd: quotient) (unsigned division) rd16 rs8 rd16 (rdh: remainder, rdl: quotient) (signed division) erd32 rs16 erd32 (ed: remainder, rd: quotient) (signed division) rd8?#xx:8 rd8?rs8 rd16?#xx:16 rd16?rs16 erd32?#xx:32 erd32?ers32 l l b b w b w b w b w b b w w l l 2 4 6 2 2 2 2 2 4 4 2 2 4 4 2 2 2 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 2 2 2 14 22 16 24 14 22 16 24 2 2 4 2 4 2 normal advanced ? ? ? ? ? * ? ? ? ? ? ? ? ? (1) (1) (2) (2) ? ? ? ? ? * ? ? ? ? ? ? ? ? ? ? (7) (7) (7) (7) ? ? (6) (6) (8) (8) ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? dec das mulxu mulxs divxu divxs cmp
appendix rev.5.00 nov. 02, 2005 page 361 of 418 rej09b0028-0500 mnemonic operation operand size addressing mode and instruction length (bytes) no. of states * 1 condition code ihnzvc #xx rn @ern @(d, ern) @?ern/@ern+ @aa @(d, pc) @@aa ? neg.b rd neg.w rd neg.l erd extu.w rd extu.l erd exts.w rd exts.l erd 0?rd8 rd8 0?rd16 rd16 0?erd32 erd32 0 ( of rd16) 0 ( of erd32) ( of rd16) ( of rd16) ( of erd32) ( of erd32) b w l w l w l 2 2 2 2 2 2 2 ? ? ? ? ? ? ? ? ? ? ? 2 2 2 2 2 2 2 normal advanced ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0 0 0 0 0 0 ? ? ? ? ? ? ? ? ? ? neg extu exts
appendix rev.5.00 nov. 02, 2005 page 362 of 418 rej09b0028-0500 3. logic instructions mnemonic operand size addressing mode and instruction length (bytes) no. of states * 1 condition code ihnzvc #xx rn @ern @(d, ern) @?ern/@ern+ @aa @(d, pc) @@aa ? and.b #xx:8, rd and.b rs, rd and.w #xx:16, rd and.w rs, rd and.l #xx:32, erd and.l ers, erd or.b #xx:8, rd or.b rs, rd or.w #xx:16, rd or.w rs, rd or.l #xx:32, erd or.l ers, erd xor.b #xx:8, rd xor.b rs, rd xor.w #xx:16, rd xor.w rs, rd xor.l #xx:32, erd xor.l ers, erd not.b rd not.w rd not.l erd operation rd8 #xx:8 rd8 rd8 rs8 rd8 rd16 #xx:16 rd16 rd16 rs16 rd16 erd32 #xx:32 erd32 erd32 ers32 erd32 rd8 ? #xx:8 rd8 rd8 ? rs8 rd8 rd16 ? #xx:16 rd16 rd16 ? rs16 rd16 erd32 ? #xx:32 erd32 erd32 ? ers32 erd32 rd8 #xx:8 rd8 rd8 rs8 rd8 rd16 #xx:16 rd16 rd16 rs16 rd16 erd32 #xx:32 erd32 erd32 ers32 erd32 ? rd8 rd8 ? rd16 rd16 ? rd32 rd32 b b w w l l b b w w l l b b w w l l b w l 2 4 6 2 4 6 2 4 6 2 2 4 2 2 4 2 2 4 2 2 2 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 2 4 2 6 4 2 2 4 2 6 4 2 2 4 2 6 4 2 2 2 normal advanced ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? and or xor not
appendix rev.5.00 nov. 02, 2005 page 363 of 418 rej09b0028-0500 4. shift instructions mnemonic operand size no. of states * 1 condition code ihnzvc shal.b rd shal.w rd shal.l erd shar.b rd shar.w rd shar.l erd shll.b rd shll.w rd shll.l erd shlr.b rd shlr.w rd shlr.l erd rotxl.b rd rotxl.w rd rotxl.l erd rotxr.b rd rotxr.w rd rotxr.l erd rotl.b rd rotl.w rd rotl.l erd rotr.b rd rotr.w rd rotr.l erd b w l b w l b w l b w l b w l b w l b w l b w l ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 normal advanced ? ? ? ? addressing mode and instruction length (bytes) #xx rn @ern @(d, ern) @?ern/@ern+ @aa @(d, pc) @@aa ? 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 operation msb lsb 0 c msb lsb 0 c c msb lsb 0c msb lsb c msb lsb c msb lsb c msb lsb c msb lsb ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? shal shar shll shlr rotxl rotxr rotl rotr
appendix rev.5.00 nov. 02, 2005 page 364 of 418 rej09b0028-0500 5. bit-manipulation instructions mnemonic operand size addressing mode and instruction length (bytes) no. of states * 1 condition code ihnzvc #xx rn @ern @(d, ern) @?ern/@ern+ @aa @(d, pc) @@aa ? bset #xx:3, rd bset #xx:3, @erd bset #xx:3, @aa:8 bset rn, rd bset rn, @erd bset rn, @aa:8 bclr #xx:3, rd bclr #xx:3, @erd bclr #xx:3, @aa:8 bclr rn, rd bclr rn, @erd bclr rn, @aa:8 bnot #xx:3, rd bnot #xx:3, @erd bnot #xx:3, @aa:8 bnot rn, rd bnot rn, @erd bnot rn, @aa:8 btst #xx:3, rd btst #xx:3, @erd btst #xx:3, @aa:8 btst rn, rd btst rn, @erd btst rn, @aa:8 bld #xx:3, rd operation (#xx:3 of rd8) 1 (#xx:3 of @erd) 1 (#xx:3 of @aa:8) 1 (rn8 of rd8) 1 (rn8 of @erd) 1 (rn8 of @aa:8) 1 (#xx:3 of rd8) 0 (#xx:3 of @erd) 0 (#xx:3 of @aa:8) 0 (rn8 of rd8) 0 (rn8 of @erd) 0 (rn8 of @aa:8) 0 (#xx:3 of rd8) ? (#xx:3 of rd8) (#xx:3 of @erd) ? (#xx:3 of @erd) (#xx:3 of @aa:8) ? (#xx:3 of @aa:8) (rn8 of rd8) ? (rn8 of rd8) (rn8 of @erd) ? (rn8 of @erd) (rn8 of @aa:8) ? (rn8 of @aa:8) ? (#xx:3 of rd8) z ? (#xx:3 of @erd) z ? (#xx:3 of @aa:8) z ? (rn8 of @rd8) z ? (rn8 of @erd) z ? (rn8 of @aa:8) z (#xx:3 of rd8) c b b b b b b b b b b b b b b b b b b b b b b b b b 2 2 2 2 2 2 2 2 2 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 2 8 8 2 8 8 2 8 8 2 8 8 2 8 8 2 8 8 2 6 6 2 6 6 2 normal advanced ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? bset bclr bnot btst bld
appendix rev.5.00 nov. 02, 2005 page 365 of 418 rej09b0028-0500 mnemonic operand size addressing mode and instruction length (bytes) no. of states * 1 condition code ihnzvc #xx rn @ern @(d, ern) @?ern/@ern+ @aa @(d, pc) @@aa ? bld #xx:3, @erd bld #xx:3, @aa:8 bild #xx:3, rd bild #xx:3, @erd bild #xx:3, @aa:8 bst #xx:3, rd bst #xx:3, @erd bst #xx:3, @aa:8 bist #xx:3, rd bist #xx:3, @erd bist #xx:3, @aa:8 band #xx:3, rd band #xx:3, @erd band #xx:3, @aa:8 biand #xx:3, rd biand #xx:3, @erd biand #xx:3, @aa:8 bor #xx:3, rd bor #xx:3, @erd bor #xx:3, @aa:8 bior #xx:3, rd bior #xx:3, @erd bior #xx:3, @aa:8 bxor #xx:3, rd bxor #xx:3, @erd bxor #xx:3, @aa:8 bixor #xx:3, rd bixor #xx:3, @erd bixor #xx:3, @aa:8 operation (#xx:3 of @erd) c (#xx:3 of @aa:8) c ? (#xx:3 of rd8) c ? (#xx:3 of @erd) c ? (#xx:3 of @aa:8) c c (#xx:3 of rd8) c (#xx:3 of @erd24) c (#xx:3 of @aa:8) ? c (#xx:3 of rd8) ? c (#xx:3 of @erd24) ? c (#xx:3 of @aa:8) c (#xx:3 of rd8) c c (#xx:3 of @erd24) c c (#xx:3 of @aa:8) c c ? (#xx:3 of rd8) c c ? (#xx:3 of @erd24) c c ? (#xx:3 of @aa:8) c c (#xx:3 of rd8) c c (#xx:3 of @erd24) c c (#xx:3 of @aa:8) c c ? (#xx:3 of rd8) c c ? (#xx:3 of @erd24) c c ? (#xx:3 of @aa:8) c c (#xx:3 of rd8) c c (#xx:3 of @erd24) c c (#xx:3 of @aa:8) c c ? (#xx:3 of rd8) c c ? (#xx:3 of @erd24) c c ? (#xx:3 of @aa:8) c b b b b b b b b b b b b b b b b b b b b b b b b b b b b b 2 2 2 2 2 2 2 2 2 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 6 6 2 6 6 2 8 8 2 8 8 2 6 6 2 6 6 2 6 6 2 6 6 2 6 6 2 6 6 normal advanced ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? bld bild bist bst band biand bor bior bxor bixor
appendix rev.5.00 nov. 02, 2005 page 366 of 418 rej09b0028-0500 6. branching instructions ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? mnemonic operand size no. of states * 1 condition code ihnzvc bra d:8 (bt d:8) bra d:16 (bt d:16) brn d:8 (bf d:8) brn d:16 (bf d:16) bhi d:8 bhi d:16 bls d:8 bls d:16 bcc d:8 (bhs d:8) bcc d:16 (bhs d:16) bcs d:8 (blo d:8) bcs d:16 (blo d:16) bne d:8 bne d:16 beq d:8 beq d:16 bvc d:8 bvc d:16 bvs d:8 bvs d:16 bpl d:8 bpl d:16 bmi d:8 bmi d:16 bge d:8 bge d:16 blt d:8 blt d:16 bgt d:8 bgt d:16 ble d:8 ble d:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 normal advanced addressing mode and instruction length (bytes) #xx rn @ern @(d, ern) @?ern/@ern+ @aa @(d, pc) @@aa ? 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 operation always never c z = 0 c z = 1 c = 0 c = 1 z = 0 z = 1 v = 0 v = 1 n = 0 n = 1 n v = 0 n v = 1 z (n v) = 0 z (n v) = 1 if condition is true then pc pc+d else next; branch condition bcc
appendix rev.5.00 nov. 02, 2005 page 367 of 418 rej09b0028-0500 mnemonic operand size addressing mode and instruction length (bytes) no. of states * 1 condition code ihnzvc #xx rn @ern @(d, ern) @?ern/@ern+ @aa @(d, pc) @@aa ? jmp @ern jmp @aa:24 jmp @@aa:8 bsr d:8 bsr d:16 jsr @ern jsr @aa:24 jsr @@aa:8 rts operation pc ern pc aa:24 pc @aa:8 pc @?sp pc pc+d:8 pc @?sp pc pc+d:16 pc @?sp pc ern pc @?sp pc aa:24 pc @?sp pc @aa:8 pc @sp+ ? ? ? ? ? ? ? ? ? 2 2 4 4 2 4 2 2 2 ? ? ? ? ? ? ? ? ? 4 6 normal advanced ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 8 6 8 6 8 8 8 10 8 10 8 10 12 10 jmp bsr jsr rts
appendix rev.5.00 nov. 02, 2005 page 368 of 418 rej09b0028-0500 7. system control instructions mnemonic operand size addressing mode and instruction length (bytes) no. of states * 1 condition code ihnzvc #xx rn @ern @(d, ern) @?ern/@ern+ @aa @(d, pc) @@aa ? trapa #x:2 rte sleep ldc #xx:8, ccr ldc rs, ccr ldc @ers, ccr ldc @(d:16, ers), ccr ldc @(d:24, ers), ccr ldc @ers+, ccr ldc @aa:16, ccr ldc @aa:24, ccr stc ccr, rd stc ccr, @erd stc ccr, @(d:16, erd) stc ccr, @(d:24, erd) stc ccr, @?erd stc ccr, @aa:16 stc ccr, @aa:24 andc #xx:8, ccr orc #xx:8, ccr xorc #xx:8, ccr nop operation pc @?sp ccr @?sp pc ccr @sp+ pc @sp+ transition to power- down state #xx:8 ccr rs8 ccr @ers ccr @(d:16, ers) ccr @(d:24, ers) ccr @ers ccr ers32+2 ers32 @aa:16 ccr @aa:24 ccr ccr rd8 ccr @erd ccr @(d:16, erd) ccr @(d:24, erd) erd32?2 erd32 ccr @erd ccr @aa:16 ccr @aa:24 ccr #xx:8 ccr ccr #xx:8 ccr ccr #xx:8 ccr pc pc+2 ? ? ? b b w w w w w w b w w w w w w b b b ? 2 2 2 2 2 2 4 4 6 10 6 10 4 4 6 8 6 8 2 2 1 ? ? ? ? ? ? ? ? ? 10 2 2 2 6 8 12 8 8 10 2 6 8 12 8 8 10 2 2 2 2 normal advanced ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 14 16 trapa rte sleep ldc stc andc orc xorc nop
appendix rev.5.00 nov. 02, 2005 page 369 of 418 rej09b0028-0500 8. block transfer instructions mnemonic operand size addressing mode and instruction length (bytes) no. of states * 1 condition code ihnzvc #xx rn @ern @(d, ern) @?ern/@ern+ @aa @(d, pc) @@aa ? eepmov. b eepmov. w operation if r4l 0 then repeat @r5 @r6 r5+1 r5 r6+1 r6 r4l?1 r4l until r4l=0 else next if r4 0 then repeat @r5 @r6 r5+1 r5 r6+1 r6 r4?1 r4 until r4=0 else next ? ? 4 4 ? ? 8+ 4n * 2 normal advanced ? ? ? ? ? ? ? ? ? ?8+ 4n * 2 eepmov notes: 1. the number of states in cases wher e the instruction code and its operands are located in on-chip memory is shown here. for ot her cases see appendix a.3, number of execution states. 2. n is the value set in register r4l or r4. (1) set to 1 when a carry or borrow occurs at bit 11; otherwise cleared to 0. (2) set to 1 when a carry or borrow occurs at bit 27; otherwise cleared to 0. (3) retains its previous value when the result is zero; otherwise cleared to 0. (4) set to 1 when the adjustment produces a carry; otherwise retains its previous value. (5) the number of states required for executi on of an instruction t hat transfers data in synchronization with the e clock is variable. (6) set to 1 when the divisor is negative; otherwise cleared to 0. (7) set to 1 when the divisor is zero; otherwise cleared to 0. (8) set to 1 when the quotient is negative; otherwise cleared to 0.
appendix rev.5.00 nov. 02, 2005 page 370 of 418 rej09b0028-0500 a.2 operation code map table a.2 operation code map (1) ah al 0123456789abcdef 0 1 2 3 4 5 6 7 8 9 a b c d e f nop bra mulxu bset brn divxu bnot stc bhi mulxu bclr ldc bls divxu btst orc or.b bcc rts or xorc xor.b bcs bsr xor bor bior bxor bixor band biand andc and.b bne rte and ldc beq trapa bld bild bst bist bvc mov bpl jmp bmi eepmov addx subx bgt jsr ble mov add addx cmp subx or xor and mov instruction when most significant bit of bh is 0. instruction when most significant bit of bh is 1. instruction code: table a-2 (2) table a-2 (2) table a-2 (2) table a-2 (2) table a-2 (2) bvs blt bge bsr table a-2 (2) table a-2 (2) table a-2 (2) table a-2 (2) table a-2 (2) table a-2 (2) table a-2 (2) table a-2 (2) table a-2 (2) table a-2 (2) table a-2 (3) 1st byte 2nd byte ah bh al bl add sub mov cmp mov.b
appendix rev.5.00 nov. 02, 2005 page 371 of 418 rej09b0028-0500 table a.2 operation code map (2) ah al bh 0123456789abcdef 01 0a 0b 0f 10 11 12 13 17 1a 1b 1f 58 79 7a mov inc adds daa dec subs das bra mov mov bhi cmp cmp ldc/stc bcc or or bpl bgt instruction code: bvs sleep bvc bge table a-2 (3) table a-2 (3) table a-2 (3) add mov sub cmp bne and and inc extu dec beq inc extu dec bcs xor xor shll shlr rotxl rotxr not bls sub sub brn add add inc exts dec blt inc exts dec ble shal shar rotl rotr neg bmi 1st byte 2nd byte ah bh al bl sub adds shll shlr rotxl rotxr not shal shar rotl rotr neg
appendix rev.5.00 nov. 02, 2005 page 372 of 418 rej09b0028-0500 table a.2 operation code map (3) ah albh blch cl 0123456789abcdef 01406 01c05 01d05 01f06 7cr06 7cr07 7dr06 7dr07 7eaa6 7eaa7 7faa6 7faa7 mulxs bset bset bset bset divxs bnot bnot bnot bnot mulxs bclr bclr bclr bclr divxs btst btst btst btst or xor bor bior bxor bixor band biand and bld bild bst bist instruction when most significant bit of dh is 0. instruction when most significant bit of dh is 1. instruction code: * * * * * * * * 1 1 1 1 2 2 2 2 bor bior bxor bixor band biand bld bild bst bist notes: 1. 2. r is the register designation field. aa is the absolute address field. 1st byte 2nd byte ah bh al bl 3rd byte ch dh cl dl 4th byte ldc stc ldc ldc ldc stc stc stc
appendix rev.5.00 nov. 02, 2005 page 373 of 418 rej09b0028-0500 a.3 number of execution states the status of execution for each instruction of the h8/300h cpu and the method of calculating the number of states required for instructio n execution are shown belo w. table a.4 shows the number of cycles of each type occurring in each instruction, such as in struction fetch and data read/write. table a.3 shows the number of states required for each cycle. the total number of states required for execution of an instruction can be calculated by the following expression: execution states = i s i + j s j + k s k + l s l + m s m + n s n examples: when instruction is fetched from on-chi p rom, and an on-chip ram is accessed. bset #0, @ff00 from table a.4: i = l = 2, j = k = m = n= 0 from table a.3: s i = 2, s l = 2 number of states required for execution = 2 2 + 2 2 = 8 when instruction is fetched from on-chip rom, branch address is read from on-chip rom, and on-chip ram is used for stack area. jsr @@ 30 from table a.4: i = 2, j = k = 1, l = m = n = 0 from table a.3: s i = s j = s k = 2 number of states required for execution = 2 2 + 1 2+ 1 2 = 8
appendix rev.5.00 nov. 02, 2005 page 374 of 418 rej09b0028-0500 table a.3 number of cycles in each instruction execution status access location (instruction cycle) on-chip me mory on-chip peripheral module instruction fetch s i 2 ? branch address read s j stack operation s k byte data access s l 2 or 3 * word data access s m 2 or 3 * internal operation s n 1 note: * depends on which on-chip peripheral module is accessed. see section 20.1, register addresses (address order).
appendix rev.5.00 nov. 02, 2005 page 375 of 418 rej09b0028-0500 table a.4 number of cycles in each instruction instruction mnemonic instruction fetch i branch addr. read j stack operation k byte data access l word data access m internal operation n add add.b #xx:8, rd add.b rs, rd add.w #xx:16, rd add.w rs, rd add.l #xx:32, erd add.l ers, erd 1 1 2 1 3 1 adds adds #1/2/4, erd 1 addx addx #xx:8, rd addx rs, rd 1 1 and and.b #xx:8, rd and.b rs, rd and.w #xx:16, rd and.w rs, rd and.l #xx:32, erd and.l ers, erd 1 1 2 1 3 2 andc andc #xx:8, ccr 1 band band #xx:3, rd band #xx:3, @erd band #xx:3, @aa:8 1 2 2 1 1 bcc bra d:8 (bt d:8) brn d:8 (bf d:8) bhi d:8 bls d:8 bcc d:8 (bhs d:8) bcs d:8 (blo d:8) bne d:8 beq d:8 bvc d:8 bvs d:8 bpl d:8 bmi d:8 bge d:8 2 2 2 2 2 2 2 2 2 2 2 2 2
appendix rev.5.00 nov. 02, 2005 page 376 of 418 rej09b0028-0500 instruction mnemonic instruction fetch i branch addr. read j stack operation k byte data access l word data access m internal operation n bcc blt d:8 bgt d:8 ble d:8 bra d:16(bt d:16) brn d:16(bf d:16) bhi d:16 bls d:16 bcc d:16(bhs d:16) bcs d:16(blo d:16) bne d:16 beq d:16 bvc d:16 bvs d:16 bpl d:16 bmi d:16 bge d:16 blt d:16 bgt d:16 ble d:16 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 bclr bclr #xx:3, rd bclr #xx:3, @erd bclr #xx:3, @aa:8 bclr rn, rd bclr rn, @erd bclr rn, @aa:8 1 2 2 1 2 2 2 2 2 2 biand biand #xx:3, rd biand #xx:3, @erd biand #xx:3, @aa:8 1 2 2 1 1 bild bild #xx:3, rd bild #xx:3, @erd bild #xx:3, @aa:8 1 2 2 1 1
appendix rev.5.00 nov. 02, 2005 page 377 of 418 rej09b0028-0500 instruction mnemonic instruction fetch i branch addr. read j stack operation k byte data access l word data access m internal operation n bior bior #xx:8, rd bior #xx:8, @erd bior #xx:8, @aa:8 1 2 2 1 1 bist bist #xx:3, rd bist #xx:3, @erd bist #xx:3, @aa:8 1 2 2 2 2 bixor bixor #xx:3, rd bixor #xx:3, @erd bixor #xx:3, @aa:8 1 2 2 1 1 bld bld #xx:3, rd bld #xx:3, @erd bld #xx:3, @aa:8 1 2 2 1 1 bnot bnot #xx:3, rd bnot #xx:3, @erd bnot #xx:3, @aa:8 bnot rn, rd bnot rn, @erd bnot rn, @aa:8 1 2 2 1 2 2 2 2 2 2 bor bor #xx:3, rd bor #xx:3, @erd bor #xx:3, @aa:8 1 2 2 1 1 bset bset #xx:3, rd bset #xx:3, @erd bset #xx:3, @aa:8 bset rn, rd bset rn, @erd bset rn, @aa:8 1 2 2 1 2 2 2 2 2 2 bsr bsr d:8 bsr d:16 2 2 1 1 2 bst bst #xx:3, rd bst #xx:3, @erd bst #xx:3, @aa:8 1 2 2 2 2
appendix rev.5.00 nov. 02, 2005 page 378 of 418 rej09b0028-0500 instruction mnemonic instruction fetch i branch addr. read j stack operation k byte data access l word data access m internal operation n btst btst #xx:3, rd btst #xx:3, @erd btst #xx:3, @aa:8 btst rn, rd btst rn, @erd btst rn, @aa:8 1 2 2 1 2 2 1 1 1 1 bxor bxor #xx:3, rd bxor #xx:3, @erd bxor #xx:3, @aa:8 1 2 2 1 1 cmp cmp.b #xx:8, rd cmp.b rs, rd cmp.w #xx:16, rd cmp.w rs, rd cmp.l #xx:32, erd cmp.l ers, erd 1 1 2 1 3 1 daa daa rd 1 das das rd 1 dec dec.b rd dec.w #1/2, rd dec.l #1/2, erd 1 1 1 duvxs divxs.b rs, rd divxs.w rs, erd 2 2 12 20 divxu divxu.b rs, rd divxu.w rs, erd 1 1 12 20 eepmov eepmov.b eepmov.w 2 2 2n+2 * 1 2n+2 * 1 exts exts.w rd exts.l erd 1 1 extu extu.w rd extu.l erd 1 1
appendix rev.5.00 nov. 02, 2005 page 379 of 418 rej09b0028-0500 instruction mnemonic instruction fetch i branch addr. read j stack operation k byte data access l word data access m internal operation n inc inc.b rd inc.w #1/2, rd inc.l #1/2, erd 1 1 1 jmp jmp @ern jmp @aa:24 jmp @@aa:8 2 2 2 1 2 2 jsr jsr @ern jsr @aa:24 jsr @@aa:8 2 2 2 1 1 1 1 2 ldc ldc #xx:8, ccr ldc rs, ccr ldc@ers, ccr ldc@(d:16, ers), ccr ldc@(d:24,ers), ccr ldc@ers+, ccr ldc@aa:16, ccr ldc@aa:24, ccr 1 1 2 3 5 2 3 4 1 1 1 1 1 1 2 mov mov.b #xx:8, rd mov.b rs, rd mov.b @ers, rd mov.b @(d:16, ers), rd mov.b @(d:24, ers), rd mov.b @ers+, rd mov.b @aa:8, rd mov.b @aa:16, rd mov.b @aa:24, rd mov.b rs, @erd mov.b rs, @(d:16, erd) mov.b rs, @(d:24, erd) mov.b rs, @-erd mov.b rs, @aa:8 1 1 1 2 4 1 1 2 3 1 2 4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2
appendix rev.5.00 nov. 02, 2005 page 380 of 418 rej09b0028-0500 instruction mnemonic instruction fetch i branch addr. read j stack operation k byte data access l word data access m internal operation n mov mov.b rs, @aa:16 mov.b rs, @aa:24 mov.w #xx:16, rd mov.w rs, rd mov.w @ers, rd mov.w @(d:16,ers), rd mov.w @(d:24,ers), rd mov.w @ers+, rd mov.w @aa:16, rd mov.w @aa:24, rd mov.w rs, @erd mov.w rs, @(d:16,erd) mov.w rs, @(d:24,erd) 2 3 2 1 1 2 4 1 2 3 1 2 4 1 1 1 1 1 1 1 1 1 1 1 2 mov mov.w rs, @-erd mov.w rs, @aa:16 mov.w rs, @aa:24 mov.l #xx:32, erd mov.l ers, erd mov.l @ers, erd mov.l @(d:16,ers), erd mov.l @(d:24,ers), erd mov.l @ers+, erd mov.l @aa:16, erd mov.l @aa:24, erd mov.l ers,@erd mov.l ers, @(d:16,erd) mov.l ers, @(d:24,erd) mov.l ers, @-erd mov.l ers, @aa:16 mov.l ers, @aa:24 1 2 3 3 1 2 3 5 2 3 4 2 3 5 2 3 4 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 movfpe movfpe @aa:16, rd * 2 2 1 movtpe movtpe rs,@aa:16 * 2 2 1
appendix rev.5.00 nov. 02, 2005 page 381 of 418 rej09b0028-0500 instruction mnemonic instruction fetch i branch addr. read j stack operation k byte data access l word data access m internal operation n mulxs mulxs.b rs, rd mulxs.w rs, erd 2 2 12 20 mulxu mulxu.b rs, rd mulxu.w rs, erd 1 1 12 20 neg neg.b rd neg.w rd neg.l erd 1 1 1 nop nop 1 not not.b rd not.w rd not.l erd 1 1 1 or or.b #xx:8, rd or.b rs, rd or.w #xx:16, rd or.w rs, rd or.l #xx:32, erd or.l ers, erd 1 1 2 1 3 2 orc orc #xx:8, ccr 1 pop pop.w rn pop.l ern 1 2 1 2 2 2 push push.w rn push.l ern 1 2 1 2 2 2 rotl rotl.b rd rotl.w rd rotl.l erd 1 1 1 rotr rotr.b rd rotr.w rd rotr.l erd 1 1 1 rotxl rotxl.b rd rotxl.w rd rotxl.l erd 1 1 1
appendix rev.5.00 nov. 02, 2005 page 382 of 418 rej09b0028-0500 instruction mnemonic instruction fetch i branch addr. read j stack operation k byte data access l word data access m internal operation n rotxr rotxr.b rd rotxr.w rd rotxr.l erd 1 1 1 rte rte 2 2 2 rts rts 2 1 2 shal shal.b rd shal.w rd shal.l erd 1 1 1 shar shar.b rd shar.w rd shar.l erd 1 1 1 shll shll.b rd shll.w rd shll.l erd 1 1 1 shlr shlr.b rd shlr.w rd shlr.l erd 1 1 1 sleep sleep 1 stc stc ccr, rd stc ccr, @erd stc ccr, @(d:16,erd) stc ccr, @(d:24,erd) stc ccr,@-erd stc ccr, @aa:16 stc ccr, @aa:24 1 2 3 5 2 3 4 1 1 1 1 1 1 2 sub sub.b rs, rd sub.w #xx:16, rd sub.w rs, rd sub.l #xx:32, erd sub.l ers, erd 1 2 1 3 1 subs subs #1/2/4, erd 1
appendix rev.5.00 nov. 02, 2005 page 383 of 418 rej09b0028-0500 instruction mnemonic instruction fetch i branch addr. read j stack operation k byte data access l word data access m internal operation n subx subx #xx:8, rd subx. rs, rd 1 1 trapa trapa #xx:2 2 1 2 4 xor xor.b #xx:8, rd xor.b rs, rd xor.w #xx:16, rd xor.w rs, rd xor.l #xx:32, erd xor.l ers, erd 1 1 2 1 3 2 xorc xorc #xx:8, ccr 1 notes: 1. n: specified value in r4l. the s ource and destination operands are accessed n+1 times respectively. 2. it can not be used in this lsi.
appendix rev.5.00 nov. 02, 2005 page 384 of 418 rej09b0028-0500 a.4 combinations of instructions and addressing modes table a.5 combinations of instructions and addressing modes addressing mode mov pop, push movfpe, movtpe add, cmp sub addx, subx adds, subs inc, dec daa, das mulxu, mulxs, divxu, divxs neg extu, exts and, or, xor not bcc, bsr jmp, jsr rts trapa rte sleep ldc stc andc, orc, xorc nop data transfer instructions arithmetic operations logical operations shift operations bit manipulations branching instructions system control instructions block data transfer instructions bwl ? ? bwl wl b ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? b ? b ? ? #xx rn @ern @(d:16.ern) @(d:24.ern) @ern+/@ern @aa:8 @aa:16 @aa:24 @(d:8.pc) @(d:16.pc) @@aa:8 ? bwl ? ? bwl bwl b l bwl b bw bwl wl bwl bwl bwl b ? ? ? ? ? ? b b ? ? ? bwl ? ? ? ? ? ? ? ? ? ? ? ? ? ? b ? ? ? ? ? w w ? ? ? bwl ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? w w ? ? ? bwl ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? w w ? ? ? bwl ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? w w ? ? ? b ? ? ? ? ? ? ? ? ? ? ? ? ? ? b ? ? ? ? ? ? ? ? ? ? ? bwl ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? w w ? ? ? bwl ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? w w ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? wl ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? bw functions instructions
appendix rev.5.00 nov. 02, 2005 page 385 of 418 rej09b0028-0500 appendix b i/o port block diagrams b.1 i/o port block diagrams res goes low in a reset, and sby goes low in a reset and in standby mode. pdr pucr pmr pcr sby res pucr: port pull-up control register pmr: port mode register pdr: port data register pcr: port control register irq trgv internal data bus pull-up mos [legend] figure b.1 port 1 block diagram (p17)
appendix rev.5.00 nov. 02, 2005 page 386 of 418 rej09b0028-0500 pdr pucr pmr pcr sby res pucr: port pull-up control register pmr: port mode register pdr: port data register pcr: port control register irq internal data bus pull-up mos [legend] figure b.2 port 1 block diagram (p16 to p14)
appendix rev.5.00 nov. 02, 2005 page 387 of 418 rej09b0028-0500 pdr pucr pcr sby res pucr: port pull-up control register pdr: port data register pcr: port control register internal data bus pull-up mos [legend] figure b.3 port 1 block diagram (p12, p11)
appendix rev.5.00 nov. 02, 2005 page 388 of 418 rej09b0028-0500 pdr pucr pmr pcr sby res pucr: port pull-up control register pmr: port mode register pdr: port data register pcr: port control register internal data bus tmow timer a pull-up mos [legend] figure b.4 port 1 block diagram (p10)
appendix rev.5.00 nov. 02, 2005 page 389 of 418 rej09b0028-0500 pdr pmr pcr sby pmr: port mode register pdr: port data register pcr: port control register internal data bus txd sci3 [legend] figure b.5 port 2 block diagram (p22)
appendix rev.5.00 nov. 02, 2005 page 390 of 418 rej09b0028-0500 pdr pcr sby pdr: port data register pcr: port control register re internal data bus rxd sci3 [legend] figure b.6 port 2 block diagram (p21)
appendix rev.5.00 nov. 02, 2005 page 391 of 418 rej09b0028-0500 pdr pcr sby pdr: port data register pcr: port control register sckie internal data bus scki sci3 sckoe scko [legend] figure b.7 port 2 block diagram (p20)
appendix rev.5.00 nov. 02, 2005 page 392 of 418 rej09b0028-0500 pdr pcr sby ice sdao/sclo sdai/scli iic2 pdr: port data register pcr: port control register internal data bus [legend] figure b.8 port 5 block diagram (p57, p56)* note: * this diagram is applied to the scl and sda pins in the h8/3694n.
appendix rev.5.00 nov. 02, 2005 page 393 of 418 rej09b0028-0500 pdr pucr pmr pcr sby res pucr: port pull-up control register pmr: port mode register pdr: port data register pcr: port control register wkp internal data bus adtrg pull-up mos [legend] figure b.9 port 5 block diagram (p55)
appendix rev.5.00 nov. 02, 2005 page 394 of 418 rej09b0028-0500 pdr pucr pmr pcr sby res pucr: port pull-up control register pmr: port mode register pdr: port data register pcr: port control register wkp internal data bus pull-up mos [legend] figure b.10 port 5 block diagram (p54 to p50)
appendix rev.5.00 nov. 02, 2005 page 395 of 418 rej09b0028-0500 pdr pcr sby os3 os2 os1 os0 tmov pdr: port data register pcr: port control register internal data bus timer v [legend] figure b.11 port 7 block diagram (p76)
appendix rev.5.00 nov. 02, 2005 page 396 of 418 rej09b0028-0500 pdr pcr sby tmciv pdr: port data register pcr: port control register internal data bus timer v [legend] figure b.12 port 7 block diagram (p75)
appendix rev.5.00 nov. 02, 2005 page 397 of 418 rej09b0028-0500 pdr pcr sby tmriv pdr: port data register pcr: port control register internal data bus timer v [legend] figure b.13 port 7 block diagram (p74)
appendix rev.5.00 nov. 02, 2005 page 398 of 418 rej09b0028-0500 pdr pcr sby pdr: port data register pcr: port control register internal data bus [legend] figure b.14 port 8 block diagram (p87 to p85)
appendix rev.5.00 nov. 02, 2005 page 399 of 418 rej09b0028-0500 pdr pcr sby pdr: port data register pcr: port control register internal data bus ftioa ftiob ftioc ftiod timer w output control signals a to d [legend] figure b.15 port 8 block diagram (p84 to p81)
appendix rev.5.00 nov. 02, 2005 page 400 of 418 rej09b0028-0500 pdr pcr sby ftci pdr: port data register pcr: port control register internal data bus timer w [legend] figure b.16 port 8 block diagram (p80)
appendix rev.5.00 nov. 02, 2005 page 401 of 418 rej09b0028-0500 dec v in ch3 to ch0 a/d converter internal data bus figure b.17 port b block diagram (pb7 to pb0) b.2 port states in each operating state port reset sleep subsleep standby subactive active p17 to p14, p12 to p10 high impedance retained retained high impedance * 1 functioning functioning p22 to p20 high impedance retained retained high impedance functioning functioning p57 to p50 * 2 high impedance retained retained high impedance * 1 functioning functioning p76 to p74 high impedance retained retained high impedance functioning functioning p87 to p80 high impedance retained retained high impedance functioning functioning pb7 to pb0 high impedance high impedance high impedance high impedance high impedance high impedance notes: 1. high level output when the pull-up mos is in on state. 2. the p55 to p50 pins are applied to the h8/3694n.
appendix rev.5.00 nov. 02, 2005 page 402 of 418 rej09b0028-0500 appendix c product code lineup product classification product code model marking package code hd64f3694h hd64f3694h qfp-64 (fp-64a) h8/3694 flash memory version standard product hd64f3694fp hd64f3694fp lqfp-64 (fp-64e) hd64f3694fx hd64f3694fx lqfp-48 (fp-48f) hd64f3694fy hd64f3694fy lqfp-48 (fp-48b) hd64f3694ft hd64f3694ft qfn-48(tnp-48) hd64f3694gh hd64f3694gh qfp-64 (fp-64a) product with por & lvdc hd64f3694gfp hd64f3694gfp lqfp-64 (fp-64e) hd64f3694gfx hd64f3694gfx lqfp-48 (fp-48f) hd64f3694gfy hd64f3694gfy lqfp-48 (fp-48b) hd64f3694gft hd64f3694gft qfn-48(tnp-48) hd6433694h hd6433694( *** )h qfp-64 (fp-64a) mask rom version standard product hd6433694fp hd6433694( *** )fp lqfp-64 (fp-64e) hd6433694fx hd6433694( *** )fx lqfp-48 (fp-48f) hd6433694fy hd6433694( *** )fy lqfp-48 (fp-48b) hd6433694ft hd6433694( *** )ft qfn-48(tnp-48) hd6433694gh hd6433694g( *** )h qfp-64 (fp-64a) product with por & lvdc hd6433694gfp hd6433694g( *** )fp lqfp-64 (fp-64e) hd6433694gfx hd6433694g( *** )fx lqfp-48 (fp-48f) hd6433694gfy hd6433694g( *** )fy lqfp-48 (fp-48b) hd6433694gft hd6433694g( *** )ft qfn-48(tnp-48) hd6433693h hd6433693( *** )h qfp-64 (fp-64a) h8/3693 mask rom version standard product hd6433693fp hd6433693( *** )fp lqfp-64 (fp-64e) hd6433693fx hd6433693( *** )fx lqfp-48 (fp-48f) hd6433693fy hd6433693( *** )fy lqfp-48 (fp-48b) hd6433693ft hd6433693( *** )ft qfn-48(tnp-48) hd6433693gh hd6433693g( *** )h qfp-64 (fp-64a) product with por & lvdc hd6433693gfp hd6433693g( *** )fp lqfp-64 (fp-64e) hd6433693gfx hd6433693g( *** )fx lqfp-48 (fp-48f) hd6433693gfy hd6433693g( *** )fy lqfp-48 (fp-48b) hd6433693gft hd6433693g( *** )ft qfn-48(tnp-48)
appendix rev.5.00 nov. 02, 2005 page 403 of 418 rej09b0028-0500 product classification product code model marking package code hd6433692h hd6433692( *** )h qfp-64 (fp-64a) h8/3692 mask rom version standard product hd6433692fp hd6433692( *** )fp lqfp-64 (fp-64e) hd6433692fx hd6433692( *** )fx lqfp-48 (fp-48f) hd6433692fy hd6433692( *** )fy lqfp-48 (fp-48b) hd6433692ft hd6433692( *** )ft qfn-48(tnp-48) hd6433692gh hd6433692g( *** )h qfp-64 (fp-64a) product with por & lvdc hd6433692gfp hd6433692g( *** )fp lqfp-64 (fp-64e) hd6433692gfx hd6433692g( *** )fx lqfp-48 (fp-48f) hd6433692gfy hd6433692g( *** )fy lqfp-48 (fp-48b) hd6433692gft hd6433692g( *** )ft qfn-48(tnp-48) hd6433691h hd6433691( *** )h qfp-64 (fp-64a) h8/3691 mask rom version standard product hd6433691fp hd6433691( *** )fp lqfp-64 (fp-64e) hd6433691fx hd6433691( *** )fx lqfp-48 (fp-48f) hd6433691fy hd6433691( *** )fy lqfp-48 (fp-48b) hd6433691ft hd6433691( *** )ft qfn-48(tnp-48) hd6433691gh hd6433691g( *** )h qfp-64 (fp-64a) product with por & lvdc hd6433691gfp hd6433691g( *** )fp lqfp-64 (fp-64e) hd6433691gfx hd6433691g( *** )fx lqfp-48 (fp-48f) hd6433691gfy hd6433691g( *** )fy lqfp-48 (fp-48b) hd6433691gft hd6433691g( *** )ft qfn-48(tnp-48) hd6433690h hd6433690( *** )h qfp-64 (fp-64a) h8/3690 mask rom version standard product hd6433690fp hd6433690( *** )fp lqfp-64 (fp-64e) hd6433690fx hd6433690( *** )fx lqfp-48 (fp-48f) hd6433690fy hd6433690( *** )fy lqfp-48 (fp-48b) hd6433690ft hd6433690( *** )ft qfn-48(tnp-48) hd6433690gh hd6433690g( *** )h qfp-64 (fp-64a) product with por & lvdc hd6433690gfp hd6433690g( *** )fp lqfp-64 (fp-64e) hd6433690gfx hd6433690g( *** )fx lqfp-48 (fp-48f) hd6433690gfy hd6433690g( *** )fy lqfp-48 (fp-48b) hd6433690gft hd6433690g( *** )ft qfn-48(tnp-48)
appendix rev.5.00 nov. 02, 2005 page 404 of 418 rej09b0028-0500 product classification product code model marking package code flash memory version hd64n3694gfp hd64n3694gfp lqfp-64 (fp-64e) h8/3694n eeprom stacked version mask rom version product with por & lvdc HD6483694Gfp HD6483694G( *** )fp lqfp-64 (fp-64e) legend: ( *** ): rom code. por & lvdc: power-on reset and low-voltage detection circuits.
appendix rev.5.00 nov. 02, 2005 page 405 of 418 rej09b0028-0500 appendix d package dimensions the package dimensions that are shown in the renesas semiconductor packages data book have priority. 1.0 11.8 12.0 12.2 1.45 10 reference symbol dimension in millimeters min nom max 0.3 0.5 0.7 previous code jeita package code renesas code fp-64e/fp-64ev 10 mass[typ.] 0.4g h l e c a d e a h a b b c x y z z l 2 d e 1 p 1 1 d e 1 12.2 12.0 11.8 1.70 0.12 0.17 0.22 0.17 0.22 0.27 0.00 0.20 0.15 0.10 0.20 0 8 0.5 0.10 0.08 1.25 1.25 p-lqfp64-10x10-0.50 plqp0064kc-a f y m x 33 48 32 49 16 17 1 64 d e d e p * 3 * 2 * 1 index mark d h e h z z b detail f 1 1 2 c l a l a a 1 1 p terminal cross section b c b c e note) 1. dimensions" * 1"and" * 2" do not include mold flash 2. dimension" * 3"does not include trim offset. figure d.1 fp-64e package dimensions
appendix rev.5.00 nov. 02, 2005 page 406 of 418 rej09b0028-0500 prqp0064gb-a p-qfp64-14x14-0.80 0.8 1.0 1.0 0.15 0.10 8 0 0.25 0.10 0.15 0.35 0.00 0.45 0.37 0.29 0.22 0.17 0.12 3.05 16.9 17.2 17.5 d 1 e d 1 1 p 1 e d 2 l z z y x c b b a h a e a c e l h 1.2g mass[typ.] fp-64a/fp-64av renesas code jeita package code previous code 1.1 0.8 0.5 max nom min dimension in millimeters symbol reference 14 2.70 17.5 17.2 16.9 1.6 14 note) 1. dimensions"*1"and"*2" do not include mold flash 2. dimension"*3"does not include trim offset. * 1 * 2 * 3 p e d e d xm y f 64 1 17 16 49 48 32 33 z z d h e h b 2 1 1 detail f c a a l a l terminal cross section p 1 1 c b c b e figure d.2 fp-64a package dimensions
appendix rev.5.00 nov. 02, 2005 page 407 of 418 rej09b0028-0500 plqp0048ja-a p-lqfp48-10x10-0.65 1.425 10 11.812.012.2 0.13 0.6 0.5 0.4 0.15 0.30 10 1.45 12.2 12.0 11.8 1.70 0.15 0.1 0.05 0.37 0.32 0.27 0.22 0.17 0.12 0.65 8 0 0.10 1.0 1.425 fp-48f/fp-48fv renesas code jeita package code previous code max nom min dimension in millimeters symbol reference 0.4g mass[typ.] 1 e d 1 1 p 1 e d 2 l z z y x c b b a h a e d a c e l h e index mark * 1 * 2 * 3 y m x f 48 112 13 37 36 24 25 d e d e p b z z h h d e detail f 1 1 2 c a l a l a 1 1 p terminal cross section b c c b note) 1. dimensions" * 1"and" * 2" do not include mold flash 2. dimension" * 3"does not include trim offset. figure d.3 fp-48f package dimensions
appendix rev.5.00 nov. 02, 2005 page 408 of 418 rej09b0028-0500 plqp0048kc-a p-lqfp48-7x7-0.50 h l e c a d e a h a b b c x y z z l 2 d e 1 p 1 1 d e 1 mass[typ.] 0.2g reference symbol dimension in millimeters min nom max previous code jeita package code renesas code fp-48b/fp-48bv 1.0 0.08 0 8 0.5 0.12 0.17 0.22 0.17 0.22 0.27 0.03 0.10 0.17 1.70 8.8 9.0 9.2 1.40 7 0.20 0.15 0.4 0.5 0.6 0.08 9.2 9.0 8.8 0.75 7 0.75 note) 1. dimensions" * 1"and" * 2" do not include mold flash 2. dimension" * 3"does not include trim offset. * 1 * 2 * 3 p e d e d 48 1 y m x f 13 12 37 36 24 25 d h e h b z z 1 2 1 detail f c a a l a l terminal cross section 1 1 p b c c b e figure d.4 fp-48b package dimensions
appendix rev.5.00 nov. 02, 2005 page 409 of 418 rej09b0028-0500 0.22 0.17 0.15 0.12 0.75 0.75 0.20 0.20 0.20 0.04 0.02 0.005 0.90 0.47 0.35 0.23 7.0 7.0 7.2 0.05 7.2 1.00 0.27 0.22 0.17 0.5 0.05 reference symbol dimension in millimeters min nom max pvqn0048ka-a p-vqfn48-7x7-0.50 0.1g mass[typ.] tnp-48/tnp-48v renesas code jeita package code previous code t 1 y p e d 1 1 2 l z z y x b b a a e d a e 1 e d c h c h e 1 b 1 y t x4 1 13 24 12 48 37 25 36 e d d e y c 1 1 2 p d h e h z z c a a a b l m figure d.5 tnp-48 package dimensions
appendix rev.5.00 nov. 02, 2005 page 410 of 418 rej09b0028-0500 appendix e eeprom stacked-structure cross-sectional view figure e.1 eeprom stacked-structure cross-sectional view
rev.5.00 nov. 02, 2005 page 411 of 418 rej09b0028-0500 main revisions and add itions in this edition item page revision (s ee manual for details) preface vi, vii notes: when using the on-chip emulator (e7, e8) for h8/3694 program development and debugging, the fo llowing restrictions must be noted. 1. the nmi pin is reserved for the e7 or e8, and cannot be used. 3. area h'7000 to h'7fff is used by the e7 or e8, and is not available to the user. 5. when the e7 or e8 is used, address breaks can be set as either available to the user or for use by the e7 or e8. if address breaks are set as being used by the e7 or e8, the address break control registers must not be accessed. 6. when the e7 or e8 is used, nmi is an input/output pin (open-drain in output mode), p85 and p87 are input pins, and p86 is an output pin. note has been deleted. section 1 overview figure 1.1 internal block diagram of h8/3694 group of f-ztat tm and mask-rom versions, figure 1.2 internal block diagram of h8/3694n (eeprom stacked version) 4, 5 pb0/an0 pb1/an1 pb2/an2 pb3/an3 pb4/an4 pb5/an5 pb6/an6 pb7/an7 iic2 timer v por/lvd (optional) port b av cc a/d converter data bus (upper) address bus
rev.5.00 nov. 02, 2005 page 412 of 418 rej09b0028-0500 item page revision (s ee manual for details) section 5 clock pulse generators figure 5.3 typical connection to crystal resonator 70 1 2 c 1 c 2 osc osc 12 c = c = 10 to 22 pf 12 figure 5.5 typical connection to ceramic resonator 71 osc 1 osc 2 c 1 c 2 c 1 = 5 to 30 pf c 2 = 5 to 30 pf bit bit name description 3 nesel noise eliminat ion sampling frequency select the subclock pulse gener ator generates the watch clock signal ( w ) and the system clock pulse generator generates the oscillator clock ( osc ). this bit selects the sampling frequency of the oscillator clock when the watch clock signal ( w ) is sampled. when osc = 4 to 20 mhz, clear nesel to 0. section 6 power-down modes 6.1.1 system control register 1 (syscr1) 76 section 8 ram 107 note: * when the e7 or e8 is used, area h'f780 to h'fb7f must not be accessed. bit bit name description 4 tcsrwe timer control/status register wd write enable section 13 watchdog timer 13.2.1 timer control/status register wd (tcsrwd) 184
rev.5.00 nov. 02, 2005 page 413 of 418 rej09b0028-0500 item page revision (s ee manual for details) bit bit name description 3 stop stop condition detection flag [setting conditions] ? in master mode, when a stop condition is detected after frame transfer ? in slave mode, when a stop condition is detected after the general call address or the first byte slave address, next to detection of start condi tion, accords with the address set in sar section 15 i 2 c bus interface 2 (iic2) 15.3.5 i 2 c bus status register (icsr) 242 15.7 usage notes 264 added section 16 a/d converter 16.3.1 a/d data registers a to d (addra to addrd) 268 therefore byte access to addr should be done by reading the upper byte first then the lower one. word access is also possible. addr is initialized to h'0000. section 18 power-on reset and low-voltage detection circuits (optional) figure 18.1 block diagram of power-on reset circuit and low- voltage detection circuit 290 res c res values item symbol applicable pins test condition min v cc = 4.0 to 5.5 v v cc 0.7 input high voltage v ih pb0 to pb7 v cc 0.8 v cc = 4.0 to 5.5 v ?0.3 input low voltage v il rxd,scl, sda, p10 to p12, : p80 to p87 pb0 to pb7 ?0.3 section 21 electrical characteristics table 21.2 dc characteristics (1) 318
rev.5.00 nov. 02, 2005 page 414 of 418 rej09b0028-0500 item page revision (s ee manual for details) mode res pin internal state active mode 1 operates active mode 2 v cc operates ( osc/64) sleep mode 1 only timers operate sleep mode 2 v cc only timers operate ( osc/64) table 21.2 dc characteristics (1) 321 values item symbol applicable pins test condition min v cc = 4.0 to 5.5 v v cc 0.7 input high voltage v ih pb0 to pb7 v cc 0.8 v cc = 4.0 to 5.5 v ?0.3 input low voltage v il rxd, scl, sda p10 to p12, : p80 to p87 pb0 to pb7 ?0.3 337 mode res pin internal state active mode 1 operates active mode 2 v cc operates ( osc/64) sleep mode 1 only timers operate sleep mode 2 v cc only timers operate ( osc/64) table 21.12 dc characteristics (1) 340 figure 21.4 i 2 c bus interface input/output timing 352 scl t stah p * s * t sf t scl t sclh t scll appendix d package dimensions 405 to 409 swapped with new ones.
rev.5.00 nov. 02, 2005 page 415 of 418 rej09b0028-0500 index a a/d converter ......................................... 265 sample-and-hold circuit...................... 272 scan mode........................................... 271 single mode ........................................ 271 address break ........................................... 63 addressing modes..................................... 34 absolute address................................... 36 immediate ............................................. 36 memory indirect ................................... 37 program-counter relative ...................... 36 register direct....................................... 35 register indirect.................................... 35 register indirect w ith displacement...... 35 register indirect with post-increment... 35 register indirect with pre-decrement.... 36 c clock pulse generators.............................. 69 prescaler s ............................................ 73 prescaler w........................................... 73 subclock generator ............................... 72 system clock generator......................... 70 condition fi eld.......................................... 33 condition-code register (ccr)................. 19 cpu .......................................................... 13 e eeprom................................................ 277 acknowledge ...................................... 281 acknowledge polling.......................... 284 byte write ........................................... 283 current address read ........................... 285 eeprom interface ............................. 280 page write ........................................... 283 random address read .......................... 286 sequential read.................................... 286 slave address reference register (esar)................................................ 281 slave addressing.................................. 281 start cond ition..................................... 280 stop condition ..................................... 281 effective address....................................... 38 effective address extension....................... 33 exception handling ................................... 49 reset exception handling ...................... 56 trap instruction..................................... 49 f flash memory ........................................... 87 boot mode............................................. 93 boot program ........................................ 93 erase/erase-verify ............................... 100 erasing units ......................................... 87 error protection................................... 103 hardware protection............................ 103 power-down st ate................................ 104 program/program-verify ....................... 98 programmer mode............................... 104 programming units................................ 87 programming/erasing in user program mode ....................................... 96 software protection............................. 103 g general registers ....................................... 18 i i/o ports .................................................. 109
rev.5.00 nov. 02, 2005 page 416 of 418 rej09b0028-0500 i/o port block diagrams ...................... 385 i 2 c bus data format ................................. 246 i 2 c bus interface 2 (iic2) ....................... 231 acknowledge...................................... 247 bit synchronous circuit....................... 263 clocked synchronous serial format..... 255 noise canceler .................................... 257 slave address ...................................... 246 start cond ition .................................... 246 stop condition..................................... 247 transfer rate........................................ 235 instruction set ........................................... 24 arithmetic operations instructions........ 26 bit manipulation instructions ............... 29 block data transfer instructions ............ 33 branch instructions ............................... 31 data transfer instructions...................... 25 logic operations instructions................ 28 shift instructions................................... 28 system control instructions................... 32 internal power supply step- down circuit ............................................ 299 interrupt internal interrupts ................................. 58 interrupt response time ......................... 60 irq3 to irq0 interrupts ....................... 57 nmi interrupt ........................................ 57 wkp5 to wkp0 interrupts ................... 57 interrupt mask bit (i)................................. 19 l large current ports...................................... 2 low-voltage detec tion circuit ................. 289 lvdi ...................................................... 295 lvdi (interrupt by low voltage detect) circuit...................................................... 295 lvdr ..................................................... 294 lvdr (reset by low voltage detect) circuit .......................................... 294 m memory map............................................. 14 module standby function .......................... 86 o on-board programming modes ................. 93 operation field .......................................... 33 p package ....................................................... 3 package dimensions................................ 405 pin arrangement .......................................... 6 power-down modes................................... 75 sleep mode............................................ 83 standby mode ....................................... 83 subactive mode..................................... 84 subsleep mode ...................................... 83 power-on reset ........................................ 289 power-on reset circuit ............................. 293 product code lineup ................................ 402 program counter (pc) ............................... 19 r register abrkcr...................... 64, 304, 309, 312 abrksr ...................... 65, 304, 309, 312 adcr ......................... 270, 304, 308, 312 adcsr ....................... 269, 304, 308, 312 addra ...................... 268, 303, 308, 312 addrb ...................... 268, 304, 308, 312 addrc ...................... 268, 304, 308, 312 addrd ...................... 268, 304, 308, 312 barh ........................... 66, 304, 309, 312 barl............................ 66, 304, 309, 312 bdrh ........................... 66, 304, 309, 312 bdrl............................ 66, 304, 309, 312 brr ............................ 198, 303, 308, 312
rev.5.00 nov. 02, 2005 page 417 of 418 rej09b0028-0500 ebr1 ............................ 91, 303, 308, 311 ekr ............................ 279, 306, 310, 313 fenr............................ 92, 303, 308, 311 flmcr1....................... 89, 303, 308, 311 flmcr2....................... 90, 303, 308, 311 flpwcr ...................... 92, 303, 308, 311 gra............................ 165, 302, 307, 311 grb............................ 165, 303, 307, 311 grc............................ 165, 303, 307, 311 grd............................ 165, 303, 307, 311 iccr1......................... 234, 302, 307, 311 iccr2......................... 236, 302, 307, 311 icdrr........................ 245, 302, 307, 311 icdrs ................................................ 245 icdrt ........................ 245, 302, 307, 311 icier.......................... 239, 302, 307, 311 icmr.......................... 237, 302, 307, 311 icsr ........................... 241, 302, 307, 311 iegr1........................... 51, 306, 309, 313 iegr2........................... 52, 306, 309, 313 ienr1........................... 53, 306, 309, 313 irr1 ............................. 54, 306, 309, 313 iwpr ............................ 55, 306, 309, 313 lvdcr....................... 290, 302, 307, 311 lvdsr ....................... 292, 302, 307, 311 mstcr1....................... 79, 306, 309, 313 pcr1........................... 111, 305, 309, 313 pcr2........................... 115, 305, 309, 313 pcr5........................... 119, 305, 309, 313 pcr7........................... 124, 305, 309, 313 pcr8........................... 126, 305, 309, 313 pdr1 .......................... 111, 305, 309, 312 pdr2 .......................... 115, 305, 309, 312 pdr5 .......................... 119, 305, 309, 312 pdr7 .......................... 124, 305, 309, 312 pdr8 .......................... 127, 305, 309, 312 pdrb.......................... 130, 305, 309, 312 pmr1.......................... 110, 305, 309, 313 pmr5.......................... 118, 305, 309, 313 pucr1........................ 112, 305, 309, 312 pucr5 ........................ 120, 305, 309, 312 rdr ............................ 192, 303, 308, 312 rsr..................................................... 192 sar............................. 244, 302, 307, 311 scr3........................... 194, 303, 308, 312 smr ............................ 193, 303, 308, 312 ssr ............................. 196, 303, 308, 312 syscr1........................ 76, 306, 309, 313 syscr2........................ 78, 306, 309, 313 tca ............................ 134, 303, 308, 312 tcnt .......................... 164, 302, 307, 311 tcntv ....................... 139, 303, 308, 312 tcora....................... 139, 303, 308, 311 tcorb ....................... 139, 303, 308, 311 tcrv0........................ 140, 303, 308, 311 tcrv1........................ 143, 303, 308, 312 tcrw......................... 158, 302, 307, 311 tcsrv........................ 142, 303, 308, 311 tcsrwd.................... 184, 304, 308, 312 tcwd......................... 185, 304, 308, 312 tdr ............................ 192, 303, 308, 312 tierw........................ 159, 302, 307, 311 tior0 ......................... 161, 302, 307, 311 tior1 ......................... 163, 302, 307, 311 tma............................ 133, 303, 308, 312 tmrw ........................ 157, 302, 307, 311 tmwd........................ 186, 304, 309, 312 tsr ..................................................... 192 tsrw ......................... 160, 302, 307, 311 register field............................................. 33 s serial communication interface 3 (sci3) ..................................................... 189 asynchronous mode............................ 205 bit rate................................................. 198 break................................................... 229 clocked synchronous mode ................ 213 framing error ...................................... 209
rev.5.00 nov. 02, 2005 page 418 of 418 rej09b0028-0500 mark state ........................................... 229 multiprocessor communication function............................................... 221 overrun error ...................................... 209 parity error.......................................... 209 stacked-structure cross sectional view of h8/3694n .................................. 410 stack pointer (sp)..................................... 19 t timer a .................................................. 131 timer v................................................... 137 timer w.................................................. 153 v vector address........................................... 49 w watchdog timer....................................... 183
renesas 16-bit single-chip microcomputer hardware manual h8/3694 group publication date: 1st edition, jul, 2001 rev.5.00, nov. 02, 2005 published by: sales strategic planning div. renesas technology corp. edited by: customer support department global strategic communication div. renesas solutions corp. ? 2005. renesas technology corp. all rights reserved. printed in japan.
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h8/3694group rej09b0028-0500 hardware manual 1753, shimonumabe, nakahara-ku, kawasaki-shi, kanagawa 211-8668 japan

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